NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 152 of 1441
NXP Semiconductors
UM10503
Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)
•
Bit 4 selects the functionality of the SCT outputs connected to the CTOUT_n pins and
selected GIMA inputs:
–
SCTimer/PWM
output Red with timer match output (default).
–
SCTimer/PWM
output only.
•
Bits 15:12 control the I2S clock connections. See also Table 1013 and Table 1014 .
•
Bit 16 controls the external memory controller clocking.
See
Section 23.2
.
Table 105. CREG6 control register (CREG6, address 0x4004 312C) bit description
Bit Symbol Value Description Reset
value Access
2:0 ETHMODE Selects the Ethernet mode. Reset the ethernet after changing
the PHY interface.
All other settings are reserved.
R/W
0x0 MII
0x4 RMII
3 - Reserved. R/W
4 CTOUTCTRL Selects the functionality of the SCTimer/PWM outputs. 0 R/W
0 Combine SCT and timer match outputs. SCTimer/PWM
outputs are Red with timer outputs.
1 SCTimer/PWM outputs only. SCTimer/PWM outputs are used
without timer match outputs.
11:5 - Reserved. - -
12 I2S0_TX_SCK_IN_SEL I2S0_TX_SCK input select 0 R/W
0 I2S Register. I2S clock selected as defined by the I2S
transmit mode register.
1 BASE_AUDIO_CLK for I2S transmit clock MCLK input and
MCLK output. The I2S must be configured in slave mode.
13 I2S0_RX_SCK_IN_SEL I2S0_RX_SCK input select 0 R/W
0 I2S Register. I2S clock selected as defined by the I2S receive
mode register.
1 BASE_AUDIO_CLK for I2S receive clock MCLK input and
MCLK output. The I2S must be configured in slave mode.
14 I2S1_TX_SCK_IN_SEL I2S1_TX_SCK input select 0 R/W
0 I2S register. I2S clock selected as defined by the I2S transmit
mode register.
1 BASE_AUDIO_CLK for I2S transmit clock MCLK input and
MCLK output. The I2S must be configured in slave mode.
15 I2S1_RX_SCK_IN_SEL I2S1_RX_SCK input select 0 R/W
0 I2S register. I2S clock selected as defined by the I2S receive
mode register.
1 BASE_AUDIO_CLK for I2S receive clock MCLK input and
MCLK output. The I2S must be configured in slave mode.
16 EMC_CLK_SEL EMC_CLK divided clock select. 0 R/W
0 Divide by 1. EMC_CLK_DIV not divided.
1 Divide by 2. EMC_CLK_DIV divided by 2.
31:17 - Reserved. - -