UM10503
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User manual
Rev. 2.1 — 10 December 2015
1357 of 1441
NXP Semiconductors
UM10503
Chapter 48: 12-bit ADC (ADCHS)
48.7.5.2.2
Slope interrupt
If, for two successive conversion results on a given channel, one result is below this
threshold and the other is equal-to or above this threshold, then a threshold crossing has
occurred. In this case the THCMP_CROSS (see
) status bits will indicate that a
threshold crossing has occurred.
A threshold crossing event will also raise interrupt flag THCMP_DCROSS for downward
crossing or THCMP_UCROSS for upward crossings and may generate an interrupt 1
request if enabled to do so via the SET_EN1 bits associated with each channel in the
SET_EN1 register.
48.7.5.3 FIFO status interrupts
An Interrupt can be raised at a defined FIFO level. See
.
48.7.6 ADC external triggers
Conversions on the 12-bit ADC can be triggered by multiple external and internal sources.
The trigger source and trigger detection logic is defined by the GIMA (see
The
ADCHS_TRIGGER_IN
register (
) selects one out of nine external
signals as hardware ADC trigger.
The trigger signal is inverted if INVERT is set, edge detected if EDGE is set and
synchronized if SYNC is set.
When SYNC is used no additional synchronization should be used (TRIGGER_SYNC
should be cleared). SYNC should be set when EDGE detection is set. Synchronization
includes two to three additional cycles latency.
Input pulses with duration less than 2 fADC cycles may not be always detected.
Fig 190. Threshold detection
THR_LOW
THR_HIGH
Bel ow Range
Ab ove Range
downward crossing
upward crossing
ADC out
time
In Range
