UM10503
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User manual
Rev. 2.1 — 10 December 2015
1008 of 1441
NXP Semiconductors
UM10503
Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with
31.3.24 SCT fractional match reload registers 0 to 5
A Fractional Match register (L, H, or unified 32-bit) is loaded from the corresponding
Fractional Match Reload register when BIDIR is 0 and the counter reaches its limit
condition, or BIDIR is 1 and the counter reaches 0, unless the appropriate NORELOAD bit
is set.
An alternate addressing mode is available for all Fractional Match Reload registers for
DMA access to halfword registers when UNIFY=0. See
.
31.3.25 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.
Each Capture Control register (L, H, or unified 32-bit) controls which events load the
corresponding Capture register from the counter.
31.3.26 SCT event state mask registers 0 to 15
Each event has one associated SCT event state mask register that allows this event to
happen in one or more states of the counter selected by the HEVENT bit in the
corresponding EVCTRLn register.
An event n is disabled when its EVSTATEMSKn register contains all zeros, since it is
masked regardless of the current state.
Table 771. SCT fractional match reload registers 0 to 5 (FRACMATREL[0:5], address 0x4000
0240 (FRACMATREL0) to 0x4000 0254 (FRACMATREL5) bit description
Bit
Symbol
Description
Reset
value
3:0
RELFRAC_L When UNIFY = 0, read or write the 4-bit value to be loaded into the
FRACMATn_L register. When UNIFY = 1, read or write the lower 4
bits to be loaded into the FRACMATn register.
0
15:4
-
Reserved.
-
19:16 RELFRAC_H When UNIFY = 0, read or write the 4-bit value to be loaded into the
FRACMATn_H register. When UNIFY = 1, read or write the upper 4
bits with the 4-bit value to be loaded into the FRACMATn register.
0
31:20 -
Reserved.
-
Table 772. SCT capture control registers 0 to 15 (CAPCTRL- address 0x4000 0200
(CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1)
Bit
Symbol
Description
Reset
value
15:0
CAPCON_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 15 = bit 15).
0
31:16
CAPCON_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0)
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
15 = bit 31).
0
