UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
984 of 1441
NXP Semiconductors
UM10503
Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)
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When the counters are stopped, both an event configured to clear the STOP bit or
software writing a zero to the STOP bit can start the counter again.
–
When the counter are halted, only a software write to clear the HALT bit can start
the counter again. No events can occur.
–
When the counters are halted, software can set any SCT output HIGH or LOW
directly by writing to the OUT register.
The current state can be read at any time by reading the STATE register.
To change the current state by software (that is independently of any event occurring), set
the HALT bit and write to the STATE register to change the state value. Writing to the
STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H
bits are set) and no events can occur.
30.7.10.3 Configure the SCT without using states
The SCT can be used as standard counter/timer with external capture inputs and match
outputs without using the state logic. To operate the SCT without states, configure the
SCT as follows:
•
Write zero to the STATE register (zero is the default).
•
Write zero to the STATELD and STATEV fields in the EVCTRL registers for each
event.
•
Write 0x1 to the EVSTATEMASK register of each event. Writing 0x1 enables the
event.
In effect, the event is allowed to occur in a single state which never changes while the
counter is running.
