UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
132 of 1441
NXP Semiconductors
UM10503
Chapter 10: LPC43xx/LPC43Sxx Event router
10.6.3 Clear event enable register
The CLR_EN register clears the corresponding bits in the ENABLE register.
20
BODRESET_E
Edge detect of the BOD reset signal. The corresponding
bit in the EDGE register must be 0.
0
0
Level detect.
1
Edge detect of the reset signal. Detect falling edge if bit
20 in the HILO register is 0. Detect rising edge if bit 19 in
the HILO register is 1.
21
DPDRESET_E
Edge detect of the deep power-down reset signal. The
corresponding bit in the EDGE register must be 0.
0
0
Level detect.
1
Edge detect of the reset signal. Detect falling edge if bit
21 in the HILO register is 0. Detect rising edge if bit 21 in
the HILO register is 1.
31:22 -
-
Reserved.
Table 88.
Edge configuration register (EDGE, address 0x4004 4004) bit description
Bit
Symbol
Value Description
Reset
value
Table 89.
Clear event enable register (CLR_EN, address 0x4004 4FD8) bit description
Bit
Symbol
Description
Reset
value
0
WAKEUP0_CLREN
Writing a 1 to this bit clears the event enable bit 0 in the
ENABLE register.
-
1
WAKEUP1_CLREN
Writing a 1 to this bit clears the event enable bit 1 in the
ENABLE register.
-
2
WAKEUP2_CLREN
Writing a 1 to this bit clears the event enable bit 2 in the
ENABLE register.
-
3
WAKEUP3_CLREN
Writing a 1 to this bit clears the event enable bit 3 in the
ENABLE register.
-
4
ATIMER_CLREN
Writing a 1 to this bit clears the event enable bit 4 in the
ENABLE register.
-
5
RTC_CLREN
Writing a 1 to this bit clears the event enable bit 5 in the
ENABLE register.
-
6
BOD_CLREN
Writing a 1 to this bit clears the event enable bit 6 in the
ENABLE register.
-
7
WWDT_CLREN
Writing a 1 to this bit clears the event enable bit 7 in the
ENABLE register.
-
8
ETH_CLREN
Writing a 1 to this bit clears the event enable bit 8 in the
ENABLE register.
-
9
USB0_CLREN
Writing a 1 to this bit clears the event enable bit 9 in the
ENABLE register.
-
10
USB1_CLREN
Writing a 1 to this bit clears the event enable bit 10 in the
ENABLE register.
-
11
SDMMC_CLREN
Writing a 1 to this bit clears the event enable bit 11 in the
ENABLE register.
-
12
CAN_CLREN
Writing a 1 to this bit clears the event enable bit 12 in the
ENABLE register.
-
