UM10503
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User manual
Rev. 2.1 — 10 December 2015
1157 of 1441
NXP Semiconductors
UM10503
Chapter 41: LPC43xx/LPC43Sxx UART1
41.6.1 UART1 Receiver Buffer Register (when DLAB = 0)
The RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the
oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the RBR.
The RBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the LSR register,
and then to read a byte from the RBR.
41.6.2 UART1 Transmitter Holding Register (when DLAB = 0)
The write-only THR is the top byte of the UART1 TX FIFO. The top byte is the newest
character in the TX FIFO and can be written via the bus interface. The LSB represents the
first bit to transmit.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the THR.
The THR is write-only.
41.6.3 UART1 Divisor Latch LSB and MSB Registers (when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16x the desired baud rate. The DLL and DLM registers
together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor and DLM
contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as
division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in LCR must be one in
order to access the UART1 Divisor Latches. Details on how to select the right value for
DLL and DLM can be found later in this chapter, see
Table 952: UART1 Receiver Buffer Register when DLAB = 0 (RBR, address 0x4008 2000) bit description
Bit
Symbol Description
Reset value
7:0
RBR
Receiver Buffer.
Contains the oldest received byte in the UART1 RX FIFO.
undefined
31:8
-
Reserved, the value read from a reserved bit is not defined.
NA
Table 953: UART1 Transmitter Holding Register when DLAB = 0 (THR, address 0x4008 2000) bit description
Bit
Symbol Description
Reset value
7:0
THR
Transmit Holding Register.
Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1
transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the
transmitter is available.
NA
31:8
-
Reserved, user software should not write ones to reserved bits.
NA
