UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
605 of 1441
NXP Semiconductors
UM10503
Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)
While the EMC is running, the refresh cycle time can be adjusted to compensate for a
changing EMC_CCLK frequency. The EMC controller might skip one refresh cycle in this
case.
Always adjust the refresh cycle time so that the appropriate number of refresh cycles fit in
the refresh time. Both the number of refresh cycles and the refresh time t
REF
are given in
the SDRAM data sheet.
This register is used for all four dynamic memory chip selects. Therefore the worst case
value for all of the chip selects must be programmed.
For example, for the refresh period of 16 µs, and a EMC_CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10
-6
x 50 x 10
6
) / 16 = 50 or 0x32
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wake-up period of a reset cycle. During this period, the
EMC (and all other portions of the chip that are being clocked) run from the IRC oscillator
at 12 MHz. The IRC oscillator frequency must be used as the EMC_CCLK rate for refresh
calculations if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.
23.7.6 Dynamic Memory Read Configuration register
This register configures the dynamic memory read strategy. This register must be
modified during system initialization with a bit value RD
1. This register is accessed with
one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Remark:
Choose command delay strategy (RD = 0x1) for SDRAM operation.
See
for programming the delay value for the EMC_CLKn delay.
Table 419. Dynamic Memory Refresh Timer register (DYNAMICREFRESH, address
0x4000 5024) bit description
Bit
Symbol
Description
Reset
value
10:0
REFRESH
Refresh timer.
Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh
cycles.
0x0 = Refresh disabled (POR reset value).
0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh
cycles.
For example:
0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles.
0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles
0
31:11 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
