Mindray Passport 5-Lead, Service Manual

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Block Diagrams Theory of Operation
2 - 38 0070-00-0420 Passport 5-Lead, 5L, LT, XG Service Manual
When the host polls the D0 bit and finds it active, it then reads the PM/NIM data address.
The EPLD decodes this into a read pulse (OE*) which enables the tristate buffer, U3, driving
the data on the bus. This action also clears F/F 2, so that IRQ 5 (were it enabled), as well as
the data available bit in the status port, are immediately dropped. The data available flag is
also available to the microcontroller as BFULL, which is connected to port C. After the
microcontroller asserts new data, it waits for the BFULL line to become low, indicating that the
host has accepted the data, before asserting the next byte.
IOCHRDY Logic
The pseudo-ISA bus in the Passport differs from a true ISA configuration in the implementation
of IOCHRDY. In the Passport, a rising edge must appear on IOCHRDY while SMEMR* or
SMEMW* is active in order to complete the bus cycle. A steady high level is not sufficient.
The EPLD contains the logic shown in figure below for generation of IOCHRDY.
FIGURE 2-16 IOCHRDY Logic Diagram
The address lines SA16..SA19 are decoded to generate a signal whenever either port (data
or control) on the board is selected. The D input of F/F 4 is high whenever a read or write
occurs and the board is selected. Before a bus cycle begins, the outputs of F/F 4 and F/F 5
are both low. These flip-flops are clocked by an on board crystal oscillator, at 3.6864 MHz.
Microcontroller
The microcontroller manages the flow of data between the host and the SpO2 Module. It
consists of a 68HC705 single chip microcontroller. It operates at an oscillator frequency of
3.6864 MHz, obtained from an on board crystal oscillator. The oscillator also provides
clocking for U4.
When it is brought out of reset, an internal self test is performed, which verifies the PROM
contents and RAM operation. During this self test period, lasting several ms, bit 4 of port C,
SRST*, is configured as an output and driven low. This asserts reset to the SpO2 Module.
The PM/NIM then enters a data echo mode.
SA16
SA17
SA18
SA19
DECODER
BOARD SELECTED
68HC05
CLOCK
IOCHRDY D Q D Q
F/F 4 F/F 5
SMEMR*
SMEMW*