Mindray Passport 5-Lead, Service Manual

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Block Diagrams Theory of Operation
2 - 64 0070-00-0420 Passport 5-Lead, 5L, LT, XG Service Manual
Only 640x240 bits of memory storage is required, so very little of the much larger available
VRAM is actually used. Refresh of the memory that is being used is automatically performed
as the video data is constantly being written to.
The VRAM parallel access address is controlled by the input horizontal and vertical video
counters. The horizontal counter counts the 912 columns of the display format (640 of which
are displayed data, the remaining columns are used for horizontal retrace). The horizontal
counter is used to drive the column address of the VRAM. The horizontal counter is clocked
by the video dot clock VCLK/ and cleared by the rising edge of the input horizontal sync
signal.
Since the 8-bit input data is formatted as 4 bits for the upper split screen and 4 bits for the
lower split screen, only 4 bits of input video data is written to the VRAM in each access.
Since the video data is written in 4-bit chunks, the lower two bits of the horizontal counter is
not sent to the VRAM address.
Depending on whether the input video data is from the top 120 lines or the bottom 120 lines,
the input video data is written to the lower 4 bits or the upper 4 bits of the 8-bit VRAM input
data path respectively. Since the input video format is single bit serial, a 4-bit shift register is
used to convert the input video data to a 4-bit parallel format. An 8-bit multiplexer directs the
4-bit shift register (double-buffered to accommodate the VRAM timing) to the appropriate half
of the VRAM parallel data input.
The write-per-bit feature of the VRAM is used to mask the appropriate 4-bits of the VRAM
parallel data input such that only the corresponding 4-bits of video information is being
written. A mask of either 00001111 or 11110000 is used depending on whether the input
video data is from the upper screen or the lower screen. The mask is written to the VRAM on
the following edge of RAS/ during the block write cycle. This mask data is selected by the
same 8-bit multiplexer that controls the VRAM parallel input data.
Since the VRAM may not necessarily power up in the correct mask mode, a CBR (CAS/
before RAS/) refresh cycle needs to be performed periodically to reset the VRAM in the
default masking mode (new mask mode) for the mask data to work properly. This is done at
the beginning of every input horizontal scan line. If a output start line address clock cycle is
not needed, then a CBR cycle is initiated in its place, before the pixel data of the horizontal
scan line is written into the VRAM.
The lower 3 bits of the horizontal counter actually forms a state machine that controls the
VRAM memory cycles. The first 3 states (S0,S1, and S2) are used to strobe in the
appropriate row address of the output video stream when the need arises (the data transfer
signal DT/ and the write control signal WB/ are changed accordingly). The last 5 states are
used to write two 4-bit chunks of input video data into the VRAM.