Mindray Passport 5-Lead, Service Manual

Page: 231 / 544

Passport 5-Lead, 5L, LT, XG Service Manual 0070-00-0420 2 - 29
Theory of Operation Block Diagrams
An offset voltage, determined by the DAC, is then subtracted by the subtraction circuit. The
plethysmographic waveform consists of a small component varying along with the
physiological pulse, sitting on top of a larger pedestal. Subtraction circuit pulls off most of
this pedestal. Subtraction circuit also helps to maintain the resultant signal in the amplifier
linear region.
The residual multiplexed signal is once again processed through a microprocessor controlled
ac gain block. One of a few discrete gains is chosen for each of the two components, such
that the peak to peak size of the physiologically varying components is large enough to be
digitized with sufficient resolution.
After going through the ac gain stage the signal is sampled by sample and hold and held for
amplitude digitization. The digitization is performed under the microprocessor control of the
digital to analog converter. The DAC voltage is successively altered by the microprocessor
until it zones in on the signal being digitized. Comparator then compares signal and DAC
voltages and sends
COMPOUT signal to the digital section.
The DAC thus performs a dual function. It is used in both the subtraction and the comparator
blocks. Every 1/240 of a second, the circuit’s control functions are flipped to process the
alternate component of the multiplexed signal. The multiplexer switches signals, the two
microprocessor controlled gains are changed, if necessary, and a new digital code is sent to
the DAC for use in the subtraction circuit. After settling to it’s new value, the signal at the
input of the comparator is frozen by sample and hold circuit. The DAC is now available to be
used in the digitization. At the next 1/240 second interval, all the control signals revert to the
previous values.
Digital Section
Digital section of the board performs two distinct functions: analog section control and ISA
bus interface.
First is based on 63C09 microprocessor. Analog section is accessed by writing data into
control register. Address decoding for generating control register strobes
APOUT0
,
APOUT1
, and
APOUT2
is done by 63C09 to analog interface. The same interface is also
responsible for monitoring status lines
COMPOUT*
and
INTERF*
. 63C09 can observe the
status of these lines by reading RD0 from the assigned memory location.
ISA bus interface allows an external processor to access SRAM and to halt and clear the
63C09 processor. Shared SRAM control is achieved by allowing 32Kx8 SRAM to be
accessed by 63C09 as well as an external processor through ISA Bus. Address bus is
shared by using 63C09 TSC signal. TSC (Tri-State Control) causes 63C09 address, data,
and R/W* buffers to assume a high-impedance state. When a valid ISA bus access cycle is
detected it is synchronized using ISA IOCHRDY signal. Because ISA access cycle is
synchronized to 63C09 clock, 63C09 always has SRAM access priority over ISA bus cycle.