Mindray Passport 5-Lead, Service Manual

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Block Diagrams Theory of Operation
2 - 42 0070-00-0420 Passport 5-Lead, 5L, LT, XG Service Manual
Non-Volatile RAM
This memory made up of two 128Kx8 120 nsec. SRAMs, U2 and U3. The memories are
non-volatile due to the circuitry of Micromanager U21, Battery BT1, R17, and D4. The initial
start address of the RAMs is at 400000H and is mapped to a 2M byte space. Chip select
line 1 is used by the CPU, and will have a wait state of one cycle. Initially only 256K bytes
should be enabled.
Video RAM
The video memory consists of a 32Kx8 120 nsec. SRAM, that is initially mapped to 64K
bytes starting at 600000H. Only the lower byte of the video memory is used (8 bit bus
mode). The LCD is a 640x200 display that will be supported with the current memory size.
The memory can be expanded to a maximum of 128K bytes for larger size displays.
This memory is dual-ported to the CPU and the display controller. A variable number of wait
states will be inserted because of the asynchronous nature of the CPU accesses to video
memory. The SCT bit in Bank Address 23H, data bit D7 of the display controller should be
set to a 1 to minimize wait time.
Display Controller
The display controller, U5, is a Yamaha V6366. The clock is provided by U38, an
11.0592MHz oscillator. The LCD that is being used on the Passport project can
accommodate a 4-bit parallel data bus. Therefore, U5 is set up for 4-bit display operation.
At the clock rate, and parallel data transmission, a transaction will last for 361 nsecs., which
will meet the minimum LCD cycle time of 330 nsecs.
The display controller outputs, CSY, BLA*, BST, AC, LD.0 are used to drive a 640x200 LCD.
The display interface signals can be disabled by the LDEN* signal (port B bit 1, U1-109).
On power-up or reset, this bit is default to an input, which will automatically disable the
display, thus preventing unorganized or old data to be displayed.
Another signal BLEN* (port B bit 2, U1-110) is provided to disable the LCD bias voltage,
VEE. This signal should not be active (low) until the display controller has been initialized,
assuring proper timing signals for the LCD. This signal works similarly to the LDEN* signal,
in that on power-up or reset, the LCD is automatically disabled. Upon a power-up/reset
situation, the display controller should be initialized as soon as possible.
The display controller outputs VSY, HSY, and LD.4 are also connected to the external
interface connector , but are not used at this time.