Mindray Passport 5-Lead, Service Manual

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Passport 5-Lead, 5L, LT, XG Service Manual 0070-00-0420 2 - 43
Theory of Operation Block Diagrams
Interrupt Controller
The interrupt controller is controlled by addresses 812H to 81CH within the 4K peripheral
control block. In addition to the 16 on-chip interrupt sources (on priority level 4), 3 external
interrupts are supported (on levels 7,6, and 1). The external interrupts should be
programmed to be dedicated level-triggered mode interrupts. Currently IRQ1* is used (for
the AR-42 Recorder error line); IRQ6* and IRQ7*, which is non-maskable, is not used. The
interrupt acknowledge and autovector mode feature is not used; the interrupt controller
should be programmed to provide the interrupt vector. The upper 3 vector bits can be
programmed to anything other than 000 and 001, such that the interrupts are mapped into
user interrupt vector space.
The external and internal interrupts can be summarized as follows:
8-bit D/A Converter
The 8-bit D/A converter, U36, is connected to the upper byte of the data bus. The address of
the D/A converter is set to 720000H for byte access. This mapping is such that it falls under
the chip select 3 timing. This device requires a 240 nsec. write pulse. This is the worst case
timing on chip select 3. With 3 wait states inserted, the pulse with respect to UDS* is 241
nsec., which is barely met.
PRIORITY INTERRUPT SOURCE DESCRIPTION
7 (Highest) IRQ7* (not used)
6 IRQ6* (not used)
5 Not available
4 PB11 interrupt (SpO2) (PAR)
PB10 interrupt (not used) (RTC)
SCC1 (Front end) (52/80)
SDMA Channels Bus Error (SERIAL DMA)
IDMA Channel
SCC2 (external RS-232) (53/54)
Timer 1 (system timer) (EECS)
SCC3 (NIBP RS-232)
PB9 interrupt (recorder sync) (RSYNC)
Timer 2 (audio frequency)
SCP (ADC channel)
Timer 3 (auxiliary timer)
SMC1 (not used)
SMC2 (not used)
PB8 interrupt (keypad) (KPS*)
Error
3 Not available
2 Not available
1 IRQ1* (recorder error)