Mindray Passport 5-Lead, Service Manual

Page: 247 / 544

Passport 5-Lead, 5L, LT, XG Service Manual 0070-00-0420 2 - 45
Theory of Operation Block Diagrams
Keypad Interface
The keypad interface consists of a matrix of 8 output lines and four input lines. A maximum
of 32 keys can be supported with this arrangement. The 8 output lines, KD.0, are connected
to the upper byte of the data bus. Their address can be set to 740000H for byte access.
The four input lines, KI.0, are also connected to the upper byte of the data bus.
During the scanning of the keypad, a marching 0 is shifted through the 8 normally high
output lines. When a key on the active low output line is pressed, a corresponding 1 (note
inversion) on the normally low input lines would be generated. All key presses need to be
debounced in software.
The keypad interface can be programmed to function in an interrupt driven mode. The KPS*
signal (port B bit 8 line) is active when there are any keys pressed. This is generated by the
use of the PAL, U24. This bit can be programmed to generate an interrupt to the
microcontroller. The operation should be as follows:
• Set all keypad output lines to 0.
• Wait for KPS* to interrupt processor. (Respond before key released, dms)
• Debounce KPS*.
• Scan keypad output lines via marching 0 for key identification.
• Start key time-out for key held down mode.
• After time-out, reset all keypad output lines to 0, clear all pending interrupts and re-
enable KPS* interrupt. (If key is still pressed, another interrupt will be generated
immediately.)
Recorder Interface
The recorder is a General Scanning AR-42. Detailed programming information is contained
in the AR-42 user’s manual.
The RERR signal is recorder error. It is pulled up (RP3-5) and inverted by U11 to form RERR*.
This signal is then connected to U1-97, which is interrupt 1. Anytime RERR* is active, the
program should service the interrupt and determine what action to take. This can be an error
or this can determine if a recorder is not available. A read of the recorder status lines at
740000H will determine what case it is. The recorder interface is a 16-bit parallel interface
mapped to 760000H. In writing to the recorder, the lower byte contains the data. The lower
5 bits of the upper byte contains the address for combination commands. The recorder can
operate in either a header command/data mode when the address bits are all one’s, or a
combined command/data mode in which the address bits indicate which command is to be
performed. When possible, the combined commands should be used to minimize data
transfer.
In writing to the recorder, the processor should check the SYNC* and WRRDY* lines from
the recorder to make sure that the recorder is ready to accept data.
In reading from the recorder, the lower byte contains readback information from the
recorder.