Mindray Passport 5-Lead, Service Manual

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Block Diagrams Theory of Operation
2 - 34 0070-00-0420 Passport 5-Lead, 5L, LT, XG Service Manual
• CLKSEQ Counter
CLKSEQ signal is used by the Sequencer. To generate this signal E clock divided by 22,
which produces CLKSEQ frequency of 62.836 KHz. Signals BIT0, BIT1, BIT2, and BIT3 are
used internally for the counter.
• ISA Access Timing Control
This section is based on U37 PLD. It is responsible address and data bus arbitration and
SRAM signal timing. In order to understand system timing, it is necessary to know how
63C09 TSC signal works. TSC (Tri-State Control), when enabled, causes 63C09 address,
data, and R/W buffers to assume high impedance state. When TSC is enabled these signals
are tri-stated after the next falling edge of E clock (See and ). 63C09 signals resume valid
levels after TSC has been disabled.
When a valid ISA access occurs (MEMW* or MEMR* active during a valid address)
IOCHRDY signal is asynchronously disabled. Access is then synchronized to system clock
and, when busses are available, ISA address buffers are enabled (using signal SROE).
SRAM (SRCE* and SROE*) and data bus buffer (ISA-RD-OE*, ISA-RD-CK*, and ISA-WR-
OE*) control signals are generated next. Finally IOCHRDY is enabled, completing ISA
access cycle.
63C09 to Analog Interface
This section is based on U41 PLD. It is responsible for generating APOUT0* through
APOUT2* Control Register strobes and monitoring the status of COMPOUT* and INTERF*
signals according to the 63C09 memory map (see ). It also generates the ISA IRQ5 signal,
which is always disabled. It is pulled up on CPU board and is used to detect whether SPO2
board is present.
Static RAM
32 K x 8 Static RAM is shared by 63C09 and external processors. Software code for 63C09
processor is downloaded into SRAM via ISA bus. Static RAM is then used by 63C09
processor to fetch instructions, store data, and communicate with the external processor.
63C09 CPU
Main function of 63C09 CPU is supervision of analog signal processing and digitization.
This is accomplished by manipulating gains of C/V, AC, and DC amplification blocks and by
controlling Sequencer, DAC, Remultiplexer, and Sample and Hold sections, while monitoring
COMPOUT* and INTERF* outputs. Control of the blocks mentioned above is achieved
through Control Register.