Mindray Passport 5-Lead, Service Manual

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Passport 5-Lead, 5L, LT, XG Service Manual 0070-00-0420 2 - 37
Theory of Operation Block Diagrams
FIGURE 2-15
EPLD, U4 Block Diagram
The output of F/F 3 drives the microcontroller’s active-low reset line. Thus, if D0 is high
during this write, the microcontroller will be placed in reset. Conversely, if zero is written,
microcontroller operation will begin. This flip-flop is also cleared by RESETDRV as well as the
EPLD’s internal power-on reset logic. Thus, at power-up, the microcontroller will be held reset
until zero is written to the status port, allowing an orderly start-up. The RESETDRV signal is
filtered by R3 and C11 to minimize the possibility of false triggering due to ESD events.
When a write is made to the data port, a decoded write pulse (CK/IRQ) clocks U2, latching
the data from the bus. This same pulse also interrupts the micro-controller (U1), telling it that
new data has arrived. Also, flip-flop F/F 1 inside U4 becomes set (see figure on previous
page). The Q output of F/F 1 can be read on data bus line D1 when a read is made to the
status port address. When the microcontroller responds to the interrupt, it clears F/F 1 by
pulsing CACK* low. Thus, bit D1 at the status address acts as a “busy” flag, which becomes
set immediately after data is written, and is cleared when the microcontroller has assimilated
the data.
When the microcontroller has data to be transferred to the ISA host, it presents the data via
port A to the tristate buffer U3. It then pulses the line STRB* low, setting F/F 2 in U4. The Q
output of this flip-flop can be read in bit position D0 of the status port. Thus, the ISA host can
poll to determine when data is available. A 1K resistor, R2, limits the current when the CO2
module drives the line high.