Mindray Passport 5-Lead, Service Manual

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Block Diagrams Theory of Operation
2 - 48 0070-00-0420 Passport 5-Lead, 5L, LT, XG Service Manual
Timers
Timer 1 is designated as the system timer.
Timer 2 is used to generate the variable tone frequency to the audio circuit. The frequency
ranges from 500Hz to 1500Hz. The operation of the audio circuit should be that when no
tone is desired, timer 2 should be turned off (rather than just setting volume to be zero).
Timer 3 is used as an auxiliary timer.
External Watchdog Timer
An external watchdog timer is implemented with a DS1236, U21. The WDOG* signal is
used to strobe the watchdog (port B bit 3; normally high). The minimum watchdog timer
period is 100 ms. Thus the software needs to force a high to low transition on the WDOG*
line at least every 100 ms. The typical timeout is 400 ms and the maximum is 600 ms.
EEPROM Interface
A serial 1K bit EEPROM, U4, organized as 64 x 16 (ICT93C46) is connected to port A bits
14, 15 and port B bits 5 and 4. The interface signals are data in (EEDI), data out (EEDO),
clock (EESK), and chip select (EECS). All data clocking and shifting will be performed in
software. Consult the 93C46 data sheet for interface information.
RTC Interface
The RTC is a Dallas DS1202, U20. The RTC has a bidirectional data line (EEDI), a clock
(EESK), and a reset (RTC) line. The data line and clock line are shared with the EEPROM
interface (port A bit 14 and port B bit 5). An active high signal RTC (port B bit 10) is used to
enable the RTC for interface. Watch crystal, Y2, is a 32.768KHz clock that is connected to
inputs X1 and X2 of U20. This provides the necessary accuracy for time and date.
SpO
2
Interface
A parallel interface similar to the ISA bus is implemented. The parallel interface is only 8 bits
wide. It is attached to the lower byte of the data bus. The 8-bit ISA address space is
1Mword addressable. Thus 2M bytes address space are needed to access this space. This
is mapped into address space starting at 800000H. Currently this parallel interface is only
used to access the SpO
2
module. The SpO
2
module appears as a block of shared memory
to the CPU. Port B, bit 11 is currently connected to the SpO
2
module. Consult the SpO
2
module documentation for interface information.
Miscellaneous Inputs and Outputs
Two signals are reserved to drive LED’s: LED0* and LED1* (port A bits 2 and 3). They are
active low. Currently only LED0* is used. It drives the alarm LED.
A defib sync output DSYNC (port A bit 11) is used to provide the external defib sync signal.
This signal should be normally high. The E trigger obtained from the analog front end should
be output to this signal as soon as possible.