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After the first line is fetched, the bit-plane pointers BPLxPTH and BPLxPTL contain the
value START+40. The modulo (in this case, 0) is added to the current value of the pointer,
so when the pointer begins the data fetch for the next line, it fetches the data you want
on that line. The data for the next line begins at memory location START+40.
Data for Line 2:
Location: START+40 START+42 START+44 .....START+78
Leftmost Next Word Next Word Last Display
Display Word Word
Figure 3-11: Data Fetched for the Second Line When Modulo = 0
Note that the pointers always contain an even number, because data is fetched from the
display a word at a time.
There are two modulo registers, BPL1MOD for the odd-numbered bit-planes and BPL2MOD
for the even-numbered bit-planes. This allows for differing modules for each playfield in
dual-playfield mode. For normal applications, both BPL1MOD and BPL2MOD will be the
same.
The following example sets the modulo to 0 for a low-resolution playfield with one bit-
plane. The bit-plane is odd-numbered.
MOVE.W #0,CUSTOM ; Set modulo to 0
DATA FETCH IN HIGH-RESOLUTION MODE
When you are using high-resolution mode to display the basic playfield, you need to fetch
80 bytes for each line, instead of 40.
MODULO IN INTERLACED MODE
For interlaced mode, you must redefine the modulo, because interlaced mode uses two
separate scanning’s of the video screen for a single display of the playfield. During the
first scanning, the odd-numbered lines are fetched to the screen; and during the second
scanning, the even-numbered lines are fetched.
- Playfield Hardware 55 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...