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The following example sets DIWSTOP for a basic playfield to $F4 for the vertical position
and $C1 for the horizontal position.
LEA CUSTOM,a0 ; Get base address of custom hardware...
MOVE.W #$F4C1,DIWSTOP(a0) ; Display window stop register...
Table 3-9: DIWSTRT AND DIWSTOP Summary.
-Nominal Values- -Possible Values-
NTSC PAL MIN MAX
DIWSTRT:
VSTART $2C $2C $00 $FF
HSTART $81 $81 $00 $FF
DIWSTOP:
VSTOP $F4 $2C (=$12C) $80 $7F (=$17F)
HSTOP $C1 $C1 $00 (=$100) $FF (=$1FF)
TELLING THE SYSTEM HOW TO FETCH AND DISPLAY DATA
After defining the size and position of the display window, you need to give the system the
on screen location for data fetched from memory. To do this, you describe the horizontal
positions where each line starts and stops and write these positions to the data-fetch
registers. The data-fetch registers have a four-pixel resolution (unlike the display window
registers, which have a one-pixel resolution). Each position specified is four pixels from
the last one. Pixel 0 is position 0; pixel 4 is position 1, and so on.
The data-fetch start and display window starting positions interact with each other. It is
recommended that data-fetch start values be restricted to a programming resolution of 16
pixels (8 clocks in low-resolution mode, 4 clocks in high-resolution mode). The hardware
requires some time after the first data fetch before it can actually display the data. As a
result, there is a difference between the value of window start and data-fetch start of 4.5
color clocks.
The normal low-resolution DDFSTRT is ($0038).
The normal high-resolution DDFSTRT is ($003C).
Recall that the hardware resolution of display window start and stop is twice the hardware
resolution of data fetch:
$81
--- -8.5=$38
2
$81
--- -4.5=$3c
2
- Playfield Hardware 53 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...