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The solution is to read a chip memory or hardware register address with the processor
before testing the bit. This can easily be done with the sequence:
btst.b #DMAB_BLTDONE-8,DMACONR(a1)
btst.b #DMAB_BLTDONE-8,DMACONR(a1)
where a1 has been preloaded with the address of the hardware registers. The first "test"
of the blitter done bit may not return the correct result, but the second blit.
NOTE
Starting with the Fat Agnus the blitter busy bit has been "fixed" to be set as soon as you
write to BLTSIZE to start the blit, rather than when the blitter gets its first DMA cycle.
However, not all machines will use the newer chips, so it is best to rely on the above
method of testing.
MULTITASKING AND THE BLITTER
When a blit is in progress, none of the blitter registers should be written. For details on
arbitration of blitter access in the system, please refer to the ROM Kernel Manual. In
particular, read the discussion about the OwnBlitter() and DisownBlitter() functions. Even
after the blitter has been "owned", a blit may still be finishing up, so the blitter done flag
should be checked before using it even the first time. Use of the ROM kernel function
WaitBlit() is recommended.
You should also check the blitter done flag before using results of a blit. The blit may not
be finished, so the data may not be ready yet. This can lead to difficult to find bugs,
because a 68000 may be slow enough for a blit to finish without checking the done flag,
while a 68020, perhaps running out of its cache, may be able to get at the data before the
blitter has finished writing it.
Let us say that we have a subroutine that displays a text box on top of other imagery
temporarily. This subroutine might allocate a chunk of memory to hold the original screen
image while we are displaying our text box, then draw the text box. On exit, the
subroutine might blit the original imagery back and then free the allocated memory. If the
memory is freed before the blitter done flag is checked, some other process might allocate
that memory and store new data into it before the blit is finished, trashing the blitter
source and, thus, the screen imagery being restored.
INTERRUPT FLAG
The blitter also has an interrupt flag that is set whenever a blit finishes. This flag, INTF
BLIT, can generate a 68000 interrupt if enabled. For more information on interrupts, see
Chapter 7 "System Control Hardware."
- Blitter Hardware 181 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...