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CHIP REGISTER MAP
Each 8520 has 16 registers that you may read or write. Here is the list
of register and the access addresses of each within the memory space
dedicated to the 8520:
Register
RS3 R52 RS1 RS0 (hex) NAME MEANING
------------------------------------------------------------
0 0 0 0 0 pra Peripheral data register A
0 0 0 1 1 prb Peripheral data regigter B
0 0 1 0 2 ddra Data direction register A
0 0 1 1 3 ddrb Direction register B
0 1 0 0 4 talo Timer A low register
0 1 0 1 5 tahi Timer A high register
0 1 1 0 6 tblo Timer B low register
0 1 1 1 7 tbhi Timer B high register
1 0 0 0 8 todlow Event LSB
1 0 0 1 9 todmid Event 8-15
1 0 1 D A todhi Event S
1 0 1 1 B No connect
1 1 0 0 C sdr Serial data register
1 1 0 1 D icr Interrupt control register
1 1 1 0 E cra Control register A
I 1 1 1 F crb Control register B
SOFTWARE NOTE:
The operating system kernel has already allocated the use of
several of the 8520 timers.
CIAA, timer A - keyboard (used continuously to handshake
keystrokes). NOT AVAILABLE.
CIAA, timer B - Virtual timer device (used continuously
whenever system Exec is in control; used
for task switching, interrupts and timing).
CIAA, TOD - 50/60 Hz timer used by timer.device. The
A1000 uses power line tick. The A500 uses
vertical sync. The A2000 has a jumper
selection.
CIAB, timer A - not used
CIAB, timer B - not used
CIAB, TOD - graphics.library video beam follower. This
timer counts at the horizontal sync rate,
and is used to synchronize graphics events
to the video beam.
Note that previous editions of this chart were incorrect.
- Appendix F 319 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...