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BIT MAP OF REGISTER CRA
REG# NAME UNUSED SPMODE INMODE LOAD RUNMODE OUTMODE PBON START
E CRA unused 0=input 0=02 1=force 0=cont. 0=pulse 0=PB60FF 0=stop
unused 1=output 1=CNT load 1=one- 1=toggle 1-PB60N 1=start
(strobe) shot
|<------------Timer A Variables------------->|
All unused register bits are unaffected by a write and forced to 0 on a
read.
CONTROL REGISTER B:
BIT NAME FUNCTION
0 START 1=start Timer B, 0=stop Timer B.
This bit is automatically reset (=0) when
underflow occurs during one-shot mode.
1 PBON 1=Timer B output on PB7, 0= PB7 is normal operation.
2 OUTMODE 1=toggle, 0=pulse.
RUNMODE 1=one-shot mode, 0=continuous mode.
4 LOAD 1=force load (this is a strobe input, there is no
data storage; bit 4 will always read back a
zero and writing a 0 has no effect.)
6,5 INMODE Bits CRB6 and CRB5 select one of four possible
input modes for Timer B, as follows:
CRB6 CRB5 Mode Selected
---- ---- --------------------------
0 0 Timer B counts 02 pulses
0 1 Timer B counts positive CNT transitions
1 0 Timer B counts Timer A underflow pulses
1 1 Timer B counts Timer A underflow pulses
while CNT pin is held high.
7 ALARM 1=writing to TOD registers sets Alarm
0=writing to TOD registers sets TOD clock.
Reading TOD registers always reads TOD clock,
regardless of the state of the Alarm bit.
- 328 Appendix F -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...