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Sampled Values: 0
90
127
90
0
-90
-127
-90
To output the series of eight samples at 1 KHz (1,000 cycles per second), each full cycle is
output in 1/1000th of a second. Therefore, each individual value must be retrieved in
1/8th of that time. This translates to 1,000 microseconds per waveform or 125
microseconds per sample. To correctly produce this waveform, the period value should be:
125 microseconds/sample
Period value = ---------------------------- = 447 timing Intervals/sample
0.279365 microseconds/interval
To set the period register, you must write the period value into the register AUDxPER,
where "x" is the number of the channel you are using. For example, the following
instruction shows how to write a period value of 447 into the period register for channel 0.
SETAUDOPERIOD:
LEA CUSTOM,a0
MOVE.W #447,AUD0PER(a0)
To produce high-quality sound, avoiding aliasing distortion, you should observe the
limitations on period values that are discussed in the section below called "Producing
Quality Sound."
For the relationship between period and musical pitch, see the section at the end of the
chapter, which contains a listing of the equal-tempered musical scale.
PLAYING THE WAVEFORM
After you have defined the audio data location, length, volume and period, you can play
the waveform by starting the DMA for that audio channel. This starts the output of sound.
Once started, the DMA continues until you specifically stop it. Thus, the waveform is
played over and over again, producing the steady tone. The system uses the value in the
location registers each time it replays the waveform.
For any audio DMA to occur (or any other DMA, for that matter), the DMAEN bit in
DMACON must be set. When both DMAEN and AUDxEN are set, the DMA will start for
channel x. All these bits and their meanings are shown in Table 5-3.
- 140 Audio Hardware -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...