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THE WAIT INSTRUCTION
The WAIT instruction causes the Copper to wait until the video beam counters are equal to
(or greater than) the coordinates specified in the instruction. While waiting, the Copper is
off the bus and not using memory cycles.
The first instruction word contains the vertical and horizontal coordinates of the beam
position. The second word contains enable bits that are used to form a "mask" that tells
the system which bits of the beam position to use in making the comparison.
FIRST INSTRUCTION WORD (IR1)
Bit 0 Always set to 1.
Bits 15 - 8 Vertical beam position (called VP).
Bits 7 - 1 Horizontal beam position (called HP).
SECOND INSTRUCTION WORD (IR2)
Bit 0 Always set to 0.
Bit 15 The blitter-finished-disable bit.
Normally, this bit is a 1.
(See the "Advanced Topics" section below.)
Bits 14 - 8 Vertical position compare enable bits (called VE).
Bits 7 - 1 Horizontal position compare enable bits (called HE).
The following example WAIT instruction waits for scan line 150 ($96) with the horizontal
position masked off.
DC.W $9601,$FF00 ; Wait for line 150,
; ignore horizontal counters.
The following example WAIT instruction waits for scan line 255 and horizontal position
254. This event will never occur, so the Copper stops until the next vertical blanking
interval begins.
DC.W $FFFF,$FFFE ; Wait for line 255,
; H = 254 (ends Copper list).
To understand why position VP=$FF HP=$FE will never occur, you must look at the
comparison operation of the Copper and the size restrictions of the position information.
Line number 255 is a valid line to wait for, in fact it is the maximum value that will fit into
this field. Since 255 is the maximum number, the next line will wrap to zero (line 256 will
appear as a zero in the
- Coprocessor Hardware 17 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...