All timing is done on the basis of a "color clock," which is 279.36ns long on NTSC
machines and 281.94ns on PAL machines. If the SERPER divisor is set to the number N,
then N+1 color clocks occur between samples of the state of the input pin (for receive) or
between transmissions of output bits (for transmit). Thus SERPER=(3,579,545/baud)-1.
On a PAL machine, SERPER=(3,546,895/baud)-1. For example, the proper SERPER value
for 9600 baud on an NTSC machine is (3,579,545/9600)-1=371.
With a cable of a reasonable length, the maximum reliable rate is on the order of
150,000-250,000 bits per second. Maximum rates will vary between machines. At these
high rate it is not possible to handle the overhead of interrupts. The receiving end will
need to be in a tight read loop. Through the use of low speed control information and
high-speed bursts, a very inexpensive communication network can be built.
SETTING THE RECEIVE MODE
The number of bits that are to be received before the system tells you that the receive
register is full may be defined either as eight or nine (this allows for 8 bit transmission
with parity). In either case, the receive circuitry expects to see one start bit, eight or nine
data bits, and at least one stop bit.
Receive mode is set by bit 15 of the write-only SERPER register. Bit 15 is a 1 if you chose
nine data bits for the receive-register full signal, and a 0 if you chose eight data bits. The
normal state of this bit for most receive applications is a 0.
CONTENTS OF THE RECEIVE DATA REGISTER
The serial input data-receive register is 16 bits wide. It contains the 8 or 9 bit input data
and status bits.
The data is received, one bit at a time, into an internal serial-to-parallel shift register.
When the proper number of bit times have elapsed, the contents of this register are
transferred to the serial data read register (SERDATR) shown in Table 8-10, and you are
signalled that there is data ready for you.
Immediately after the transfer of data takes place, the receive shift register again
becomes ready to accept new data. After receiving the receiver-full interrupt, you will
have up to one full character-receive time (8 to 10 bit times) to accept the data and clear
the interrupt. If the interrupt is not cleared in time, the OVERRUN bit is set.
- Interface Hardware 251 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...
