SPR0PTH + 120 W A Sprite 0 pointer (high 3 bits)
SPR0PTL + 122 W A Sprite 0 pointer (low 15 bits)
SPR1PTH + 124 W A Sprite 1 pointer (high 3 bits)
SPR1PTL + 126 W A Sprite 1 pointer (low 15 bits)
SPR2PTH + 128 W A Sprite 2 pointer (high 3 bits)
SPR2PTL + 12A W A Sprite 2 pointer (low 15 bits)
SPR3PTH + 12C W A Sprite 3 pointer (high 3 bits)
SPR3PTL + 12E W A Sprite 3 pointer (low 15 bits)
SPR4PTH + 130 W A Sprite 4 pointer (high 3 bits)
SPR4PTL + 132 W A Sprite 4 pointer (low 15 bits)
SPR5PTH + 134 W A Sprite 5 pointer (high 3 bits)
SPR5PTL + 136 W A Sprite 5 pointer (low 15 bits)
SPR6PTH + 138 W A Sprite 6 pointer (high 3 bits)
SPR6PTL + 13A W A Sprite 6 pointer (low 15 bits)
SPR7PTH + 13C W A Sprite 7 pointer (high 3 bits)
SPR7PTL + 13E W A Sprite 7 pointer (low 15 bits)
SPR0POS % 140 W A D Sprite 0 vert-horiz start position data
SPR0CTL % 142 W A D Sprite 0 vert stop position and control data
SPR0DATA % 144 W D Sprite 0 image data register A
SPR0DATB % 146 W D Sprite 0 image data register B
SPR1POS % 148 W A D Sprite 1 vert-horiz start position data
SPR1CTL % 14A W A D Sprite 1 vert stop position and control data
SPR1DATA % 14C W D Sprite 1 image data register A
SPR1DATB % 14E W D Sprite 1 image data register B
SPR2POS % 150 W A D Sprite 2 vert-horiz start position data
SPR2CTL % 152 W A D Sprite 2 vert stop position and control data
SPR2DATA % 154 W D Sprite 2 image data register A
SPR2DATB % 156 W D Sprite 2 image data register B
SPR3POS % 158 W A D Sprite 3 vert-horiz start position data
SPR3CTL % 15A W A D Sprite 3 vert stop position and control data
SPR3DATA $ 15C W D Sprite 3 image data register A
SPR3DATB % 15E W D Sprite 3 image data register B
SPR4POS % 160 W A D Sprite 4 vert-horiz start position data
SPR4CTL % 162 W A D Sprite 4 vert stop position and control data
SPR4DATA % 164 W D Sprite 4 image data register A
SPR4DATB % 166 W D Sprite 4 image data register B
SPR5POS % 168 W A D Sprite 5 vert-horiz start position data
SPR5CTL % 16A W A D Sprite 5 vert stop position and control data
SPR5DATA % 16C W D Sprite 5 image data register A
SPR5DATB % 16E W D Sprite 5 image data register B
- 286 Appendix B -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...
