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Mem. Location N Mem. location N+38
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Mem. Location N+40 | Mem. location N+78
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Mem. Location N+7960 Mem. location N+7998
Figure 3-7: Memory Organization for a Basic Bit-Plane
Access to bit-planes in memory is provided by two address registers, BPLxPTH and
BPLxPTL, for each bit-plane (12 registers in all). The "x" position in the name holds the
bit-plane number; for example BPL1PTH and BPL1PTL hold the starting address of PLANE
1. Pairs of registers with names ending in PTH and PTL contain 19-bit addresses. 68000
programmers may treat these as one 32-bit address and write to them as one long word.
You write to the high-order word, which is the register whose name ends in "PTH."
The example below shows how to set the bit-plane pointers. Assuming two
bit-planes, one at $21000 and the other at $25000, the processor sets
BPL1PT to $21000 and BPL2PT to $25000. Note that this is usually the
Copper's task.
;
; Since the bit plane pointer registers are mapped as a full 680x0 long-
; word data, we can store the addresses with a 32-bit move...
;
LEA CUSTOM,a0 ; Get base address of custom hardware...
MOVE.L $21000,BPL1PTH(a0) ; Write bit-plane 1 pointer
MOVE.L $25000,BPL2PTH(a0) ; Write bit-plane 2 pointer
Note that the memory requirements given here are for the playfield only. You may need
to allocate additional memory for other parts of the display, sprites, audio, animation and
for your application programs. Memory allocation for other parts of the display is
discussed in the chapters describing those topics.
- 48 Playfield Hardware -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...