
DSKBYTR - DISK DATA BYTE AND STATUS READ (READ-ONLY)
This register is the disk-microprocessor data buffer. In read mode, data from the disk is
placed into this register one byte at a time. As each byte is received into the register, the
DSKBYT bit is set true. DSKBYT is cleared when the DSKBYTR register is read.
DSKBYTR may be used to synchronize the processor to the disk rotation before issuing a
read or write under DMA control.
Table 8-7: DSKBYTR Register
Bit
Number Name Function
15 DSKBYT When set, indicates that this register contains
a valid byte of data (reset by reading this
register).
14 DMAON Indicates when DMA is actually enabled. All the
various DMA bits must be true. This means the
DMAEN bit in DKSLEN, and the DSKEN & DMAEN bits in
DMACON.
13 DISKWRITE The disk write bit (in DSKLEN) is enabled.
12 WORDEQUAL Indicates the DISKSYNC register equals the disk
input stream. This bit is true only while the
input stream matches the sync register (as little
as two microseconds).
11-8 Currently unused; don't depend on read value.
7-0 DATA Disk byte data.
ADKCON AND ADKCONR - AUDIO AND DISK CONTROL REGISTER
ADKCON is the write-only address and ADKCONR is the read-only address for this register.
Not all of the bits are dedicated to the disk. Bit 15 of this register allows independent
setting or clearing of any bit or bits. If bit 15 is a one on a write, any ones in positions 0-
14 will set the corresponding bit. If bit 15 is a zero, any ones will clear the corresponding
bit.
- 242 Interface Hardware -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...