manualshive.com logo in svg

Commodore Amiga A1000, Hardware Reference Manual

Share
Download
Commodore Amiga A1000 Hardware Reference Manual Download Page 283

INTENA      09A W P Interrupt enable bits (clear or set bits)

 

INTENAR     01C R P Interrupt enable bits (read)

 

 

                 This register contains interrupt enable bits. The bit

 

                 assignment for both the request and enable registers

 

                 is given below.

 

 

                 BIT#   FUNCT  LEVEL  DESCRIPTION

 

                 --------------------------------------------------------

 

                 15    SET/CLR       Set/clear control bit. Determines if

 

                                     bits written with a 1 get set or

 

                                     cleared. Bits written with a zero

 

                                     are always unchanged.

 

                 14    INTEN         Master interrupt (enable only,

 

                                     no request)

 

                 13    EXTER     6   External interrupt

 

                 12    DSKSYN    5   Disk sync register (DSKSYNC)

 

                                      matches disk data

 

                 11    RBF       5   Serial port receive buffer full

 

                 10    AUD3      4   Audio channel 3 block finished

 

                 09    AUD2      4   Audio channel 2 block finished

 

                 08    AUDl      4   Audio channel 1 block finished

 

                 07    AUD0      4   Audio channel 0 block finished

 

                 06    BLIT      3   Blitter finished

 

                 05    VERTB     3   Start of vertical blank

 

                 04    COPER     3   Copper

 

                 03    PORTS     2   I/O ports and timers

 

                 02    SOFT      1   Reserved for software-initiated

 

                                      interrupt

 

                 01    DSKBLK    1   Disk block finished

 

                 00    TBE       1   Serial port transmit buffer empty

 

 

INTREQ       09C W       P Interrupt request bits (clear or set)

 

INTREQR      01E R       P Interrupt request bits (read)

 

 

This register contains interrupt request bits (or flags). These bits may

 

be polled by the processor; if enabled by the bits listed in the next

 

register, they may cause processor interrupts. Both a set and clear

 

operation are required to load arbitrary data into this register. These

 

status bits are not automatically reset when the interrupt is serviced,

 

and must be reset when desired by writing to this address. The bit

 

assignments are identical to the enable register below.

 

 

                            
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

- 274 Appendix A -

 

Summary of Contents for Amiga A1000

Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...

Page 2: ...HES 25 Starting and Stopping the Copper 25 STARTING THE COPPER AFTER RESET 25 STOPPING THE COPPER 26 Advanced Topics 27 THE SKIP INSTRUCTION 27 COPPER LOOPS AND BRANCHES AND COMPARISON ENABLE 28 USING...

Page 3: ...ESOLUTION MODE 88 COLOR SELECTION IN HOLD AND MODIFY MODE 90 COLOR SELECTION IN HIGH RESOLUTION MODE 90 Chapter 4 SPRITE HARDWARE 93 Introduction 93 ABOUT THIS CHAPTER 94 Forming a Sprite 94 SCREEN PO...

Page 4: ...pter 6 BLITTER HARDWARE 163 Introduction 163 Memory Layout 164 DMA Channels 164 Function Generator 168 DESIGNING THE LF CONTROL BYTE WITH MINTERMS 169 DESIGNING THE LF CONTROL BYTE WITH VENN DIAGRAMS...

Page 5: ...MITATIONS OF THE KEYBOARD 247 Parallel Input Output Interface 250 Serial Interface 250 INTRODUCTION TO SERIAL CIRCUITRY 250 SETTING THE BAUD RATE 250 SETTING THE RECEIVE MODE 251 CONTENTS OF THE RECEI...

Page 6: ...s 332 INTERFACE SIGNALS 332 Appendix G AUTOCONFIG 335 Debugging AUTOCONFIG Boards 336 Address Specification Table 337 Appendix H Keyboard 343 Keyboard Communications 344 Keycodes 345 CAPS LOCK Key 345...

Page 7: ...sition 74 Figure 3 23 Vertical Scrolling 76 Figure 3 24 Horizontal Scrolling 78 Figure 3 25 Memory Picture Larger than the Display Window 79 Figure 3 26 Data for Line 1 Horizontal Scrolling 79 Figure...

Page 8: ...Plug and Computer Connector 222 Figure 8 2 Mouse Quadrature 224 Figure 8 3 Joystick to Counter Connections 227 Figure 8 4 Typical Paddle Wiring Diagram 229 Figure 8 5 Effects of Resistance on Charging...

Page 9: ...Table 4 5 Color Registers in Attached Sprites 119 Table 4 6 Color Registers for Single Sprites 127 Table 4 7 Color Registers for Attached Sprites 128 Table 5 1 Sample Audio Data Set for Channel 0 135...

Page 10: ...use of custom silicon hardware that yields advanced graphics and sound features There are three distinct models that make up the Amiga computer family the A500 A1000 and A2000 Though the models diffe...

Page 11: ...ble controller ports for mice joysticks light pens paddles or custom controllers o A professional keyboard with numeric keypad 10 function keys and cursor keys A variety of international keyboards are...

Page 12: ...tal slices each having different video resolutions and color depths beam synchronized interrupt generation for the 68000 and more The co processor can trigger many times per screen in the middle of li...

Page 13: ...p memory The original custom chips in the Amiga were designed to be able to physically access up to 512K bytes of shared memory The new version of the Agnus custom chip was created which allows the gr...

Page 14: ...fully integrated video images with computer generated graphics Laser disk input is accepted in the same manner PERIPHERALS Floppy disk storage is provided by a built in 3 5 inch floppy disk drive Disk...

Page 15: ...the A500 or A1000 but with the added convenience of simple and extensive expandability The 86 pin external connector of the A1000 and A500 is not externally accessible on the A2000 Instead the A2000...

Page 16: ...f this manual Generally such functions when available will be found in the library device or resource which manages that portion of the Amiga hardware in the multitasking environment The following lis...

Page 17: ...y the include file label names are very similar to the equivalent hardware register list names with the following typical differences o Address registers which have low word and high word components a...

Page 18: ...de that calls routines in the F80000 to FFFFFF range These are ROM addresses and the ROM routines WILL move with every OS revision The only supported interface to system ROM code is through the provid...

Page 19: ...ch is privileged on the 68010 20 30 Use the Exec function GetCC instead of MOVE SR or use the appropriate non privileged instruction as shown below CPU User Mode Super Mode 68000 MOVE SR ea MOVE SR ea...

Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...

Page 21: ...12 Introduction...

Page 22: ...he 68000 to execute program logic it can also directly affect the contents of most of the chip control registers It is a very powerful tool for directing mid screen modifications in graphics displays...

Page 23: ...and polygon filling As with all the other DMA channels in the Amiga system the Copper can retrieve its instructions only from the chip RAM area of system memory ABOUT THIS CHAPTER In this chapter you...

Page 24: ...Copper in controlling the blitter can be found in the sections called Control Register and Using the Copper with the Blitter The WAIT and MOVE instructions are described below The SKIP instruction is...

Page 25: ...egisters It is strongly recommended that you reference all hardware addresses via their defined names in the system include files This will allow you to more easily adapt your software to take advanta...

Page 26: ...anced Topics section below Bits 14 8 Vertical position compare enable bits called VE Bits 7 1 Horizontal position compare enable bits called HE The following example WAIT instruction waits for scan li...

Page 27: ...BEAM POSITION The horizontal beam position has a value of 0 to E2 The least significant bit is not used in the comparison so there are 113 positions available for Copper operations This corresponds to...

Page 28: ...g long and short lines there are also long and short fields interlace only In NTSC the fields are 262 then 263 lines and in PAL 312 313 This alteration of lines fields produces the standard NTSC 4 fie...

Page 29: ...gnificant data or low 15 bits of the address Therefore you write the 18 bit address by moving one long word to the register whose name ends in H This is because when you write long words with the 6800...

Page 30: ...urpose registers all of the time some registers only when a special control bit is set to a 1 some registers not at all The registers that the Copper can always affect are numbered 20 through FF inclu...

Page 31: ...en during the vertical blanking interval so the data will be properly retrieved when the screen display starts again This can be done with a Copper instruction list that does the following WAIT until...

Page 32: ...value in the beam counter is equal to or greater than the value in the instruction This means for example if you have instructions following each other like this WAIT for position 64 64 MOVE data WAIT...

Page 33: ...trary 3 Destination register addresses in copper move instructions are offsets from the base address of the custom chips 4 As always hardware manual examples assume that your application has taken ful...

Page 34: ...r 0180 COLOR00 DC W COLOR01 0FF0 Move yellow into register 0182 COLOR01 DC W COLOR02 00FF Move cyan into register 0184 COLOR02 DC W COLOR03 0F0F Move magenta into register 0186 COLOR03 End Copper list...

Page 35: ...isplayed screen to be stable STOPPING THE COPPER No stop instruction is provided for the Copper To ensure that it will stop and do nothing until the screen display ends and the program counter starts...

Page 36: ...WORD IR1 Bit 0 Always set to 1 Bits 15 8 Vertical position called VP Bits 7 1 Horizontal position called HP Skip if the beam counter is equal to or greater than these combined bits bits 15 through 1...

Page 37: ...all of the bits in the beam counter may be masked If you look at the description of the IR2 second instruction word you will notice that bit 15 is the blitter finished disable bit This bit is not part...

Page 38: ...set binary 1xxx1111 This is true for both the vertical and the horizontal WAIT instructions To cause the second loop write to the COPJMP2 register The list is put into an infinite wait when VP 255 so...

Page 39: ...ed lines and one containing the odd numbered lines Figure 2 1 shows how an interlaced display is stored in memory Odd Field Even field time t time t 16 6ms Data in memory _____________ 1 _____________...

Page 40: ...ontrol the WAIT When the BFD bit is a 0 the logic of the Copper WAIT instruction is modified The Copper will WAIT until the beam counter comparison is true and the blitter has finished The blitter has...

Page 41: ...P1 VE1 VP1 VE1 08 DA8 RD08 VP0 VE0 VP0 VE0 07 DA7 RD07 HP8 HE8 HP8 HE8 06 DA6 RD06 HP7 HE7 HP7 HE7 05 DAS RD05 HP6 HE6 HP6 HE6 04 DA4 RD04 HPS HES HPS HES 03 DA3 RD03 HP4 HE4 HP4 HE4 02 DA2 RD02 HP3 H...

Page 42: ...een display consists of two basic parts playfields which are sometimes called backgrounds and sprites which are easily movable graphics objects This chapter describes how to directly access hardware r...

Page 43: ...S The Amiga produces its video displays with raster display techniques The picture you see on the screen is made up of a series of horizontal video lines displayed one after the other Each horizontal...

Page 44: ...single picture element the smallest addressable part of a screen display The drawings below show what a pixel is and how pixels form displays _______________________ _ _ The picture is formed from man...

Page 45: ...elds In the Amiga graphics system you can have up to thirty two different colors in a single playfield using normal display methods You can control the color of each individual pixel in the playfield...

Page 46: ..._________________ 00001 _______________________ 00010 _______________________ 00011 _______________________ 00100 _______________________ _______________________ 11111 _______________________ Figure 3...

Page 47: ...al playfield mode FORMING A BASIC PLAYFIELD To get you started this section describes how to directly access hardware registers to form a single basic playfield that is the same size as the video scre...

Page 48: ...on the resolution you choose The height is either 200 or 400 lines for NTSC 256 or 512 lines for PAL depending upon whether or not you choose interlaced mode BIT PLANES AND COLOR You define playfield...

Page 49: ...R02 12 bits User defined color number 2 etc etc COLOR31 12 bits User defined color number 31 COLOR00 is always reserved for the background color The background color shows in any area on the display w...

Page 50: ...W FFF COLOR00 a0 Load white into color register 0 MOVE W 6FE COLOR01 a0 Load sky blue into color register 1 NOTE The color registers are write only Only by looking at the screen can you find out the...

Page 51: ...yfield is visible Sixth bit plane is used only in dual playfield mode and in hold and modify mode described in the section called Advanced Topics NOTE The bits in the BPLCON0 register cannot be set in...

Page 52: ...ide To set horizontal resolution mode you write to bit 15 HIRES in register BPLCON0 High resolution modewrite 1 to bit 15 Low resolution modewrite 0 to bit 15 Note that in high resolution mode you can...

Page 53: ...______________________ Figure 3 5 Interlacing Even though interlaced mode requires a modest amount of extra work in setting registers as you will see later on in this section it provides fine tuning t...

Page 54: ...ts the following parameters that are also controlled through register BPLCON0 o High resolution mode is enabled o Two bit planes are used o Hold and modify mode is disabled o Single playfield mode is...

Page 55: ...plane pointer registers BPLxPTH BPLxPTL to point to the starting memory address of each bitplane you are using The starting address is the memory word that contains the bits of the upper left hand co...

Page 56: ...splay line and a total of 200 display lines each line of the bit plane requires 40 bytes 320 bits divided by 8 bits per byte 40 Multiply the 200 lines times 40 bytes per line to get 8 000 bytes per bi...

Page 57: ...as one 32 bit address and write to them as one long word You write to the high order word which is the register whose name ends in PTH The example below shows how to set the bit plane pointers Assumi...

Page 58: ...s where you want the background color and 1 s where you want the color in register 1 The following example code is identical to the last example except the bit plane is filled with FF00FF00 instead of...

Page 59: ...ize of the display window which is the actual size of the on screen display Adjustment of display window size affects the entire display area including the border and the sprites not just the playfiel...

Page 60: ...tion is 2C The horizontal and vertical starting positions are the same both for NTSC and for PAL The hardware allows you to specify a starting position before 81 2C but part of the display may not be...

Page 61: ...ing position which is the lower right hand corner of the display window If you select high resolution or interlaced mode the stopping position does not change Like the starting position it is interpre...

Page 62: ...The data fetch registers have a four pixel resolution unlike the display window registers which have a one pixel resolution Each position specified is four pixels from the last one Pixel 0 is positio...

Page 63: ...a followed by another line For the basic playfield where the playfield in memory is the same size as the display window the modulo is zero because the memory area contains exactly the same number of b...

Page 64: ...umbered bit planes and BPL2MOD for the even numbered bit planes This allows for differing modules for each playfield in dual playfield mode For normal applications both BPL1MOD and BPL2MOD will be the...

Page 65: ...rned on You turn on bit plane DMA by writing a 1 to bit BPLEN in the DMACON for DMA control register See Chapter 7 System Control Hardware for instructions on setting this register Each time The playf...

Page 66: ...ode b Specify width in pixels o 320 for low resolution mode o 640 for high resolution mode c Specify color for each pixel o Load desired colors in color table registers o Define color of each pixel in...

Page 67: ...200 vertical lines for NTSC 256 for PAL Clear bit 2 in BPLCON0 LACE 2 Allocate Memory To calculate data bytes in the total bit planes use the following formula Bytes per line lines in playfield number...

Page 68: ...e which is located at 21000 Also a Copper list is set up at 20000 This example relies on the include file hw examples i which is found in Appendix J LEA CUSTOM a0 a0 points at custom chip MOVE W 1200...

Page 69: ...PLCON0 a0 Hires one bit plane interlaced MOVE W 0 BPLCON1 a0 Horizontal scroll value 0 MOVE W 80 BPL1MOD a0 Modulo 80 for odd bit planes MOVE W 80 BPL2MOD a0 Ditto for even bit planes MOVE W 003C DDFS...

Page 70: ...to 20000 This keeps the long and short frames in the right relationship to each other VLOOP MOVE W INTREQR a0 d0 Read interrupt requests AND W 0020 d0 Mask off all but vertical blank BEQ VLOOP Loop un...

Page 71: ...set a bit to activate dual playfield mode Figure 3 12 shows a dual playfield display In Figure 3 12 one of the colors in each playfield is transparent color 0 in playfield 1 and color 8 in playfield 2...

Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...

Page 73: ...4 1 ________ _ 2 ________ _ _ 3 _ 4 __________ __________ __________ __________ 5 1 ________ _ 2 ________ _ _ 3 ________ _ _ 4 _ 5 __________ __________ __________ __________ 6 1 ________ _ 2 ________...

Page 74: ...ion Mode PLAYFIELD 1 Bit Color Combination Selected 000 Transparent mode 001 COLOR1 010 COLOR2 011 COLOR3 100 COLOR4 101 COLORS 110 COLOR6 111 COLOR7 The hardware interprets color numbers for playfiel...

Page 75: ...TY AND CONTROL Either playfield 1 or 2 may have priority that is either one may be displayed in front of the other Playfield 1 normally has priority The bit known as PF2PRI bit 6 in register BPLCON2 i...

Page 76: ...ster BPLCON0 selects dual playfield mode Selecting dual playfield mode changes both the way the hardware groups the bit planes for color interpretation all odd numbered bit planes are grouped together...

Page 77: ...following ways from displaying the basic playfields described up to now o If the big picture in memory is larger than the display window you must respecify the modules The modulo must be some value ot...

Page 78: ...eftmost Next Word Next Word Last Display Display Word Word Screen data fetch stops DDFSTOP for each horizontal line after the last word on the line has been fetched Figure 3 15 Data Fetch for the Firs...

Page 79: ...xt Word Next Word Last Display Display Word Word Figure 3 17 Data Layout for First Line Right Half of Big Picture Now the bit plane pointers contain the value START 80 The modulo 40 is added to the po...

Page 80: ...t planes it requires 80 200 2 32 000 bytes of memory Recall that this is the memory requirement for the playfield alone You need more memory for any sprites animation audio or application programs you...

Page 81: ...NTSC ____________262 Figure 3 20 Display Window Vertical Starting Position Recall that you select the values for the starting position as if the display were in low resolution non interlaced mode Kee...

Page 82: ...P contains both coordinates known as HSTOP and VSTOP See the notes in the Forming a Basic Playfield section for instructions on setting these registers FULL SCREEN AREA 0 255 361 HSTOP of DISPLAY WIND...

Page 83: ...y the restrictions are simple No data can be displayed in the vertical blanking area The following Table shows the allowable vertical display area Table 3 13 Maximum Allowable Vertical Screen Video Ve...

Page 84: ...for vertical scrolling is progressively increase or decrease the starting address for the bit plane pointers by the size of a horizontal line in the playfield This has the effect of showing a lower o...

Page 85: ...n in interlace Figure 3 23 Vertical Scrolling To set up a playfield for vertical scrolling you need to form bit planes tall enough to allow for the amount of scrolling you want write software to calcu...

Page 86: ...planes wide enough to allow for the scrolling you need o Set the data fetch registers to correctly place each horizontal line including the extra word on the screen o Set the delay bits o Set the mod...

Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...

Page 88: ...d Next Word Last Display display word word Figure 3 26 Data for Line 1 Horizontal Scrolling At this point the bit plane pointers contain the value START 42 Adding the modulo of 38 gives the correct st...

Page 89: ...CUSTOM SCROLLED PLAYFIELD SUMMARY The steps for defining a scrolled playfield are the same as those for defining the basic playfield except for the following steps o Defining the data fetch Fetch one...

Page 90: ...he hold and modify mode allows very fine gradients of color or shading to be produced on the screen For example you might draw a set of 16 vases each a different color using all 16 colors in the color...

Page 91: ...s active The following example code generates a six bit plane display with hold and modify mode turned on All 32 color registers are loaded with black to prove that the colors are being generated by h...

Page 92: ...COPPERL pc a2 Point a2 at Copper list image CLOOP MOVE L a2 a1 Move a long word CMPI L FFFFFFFE a2 Check for end of Copper list BNE CLOOP Loop until entire Cop list moved Point Copper at Copper list M...

Page 93: ...external video source For more information see the instructions furnished with the optional board SUMMARY OF PLAYFIELD REGISTERS This section summarizes the registers used in this chapter and the mean...

Page 94: ...nd modify enable 1 hold and modify enabled 0 hold and modify disabled Bits 14 13 12 BPU2 BPU1 BPU0 Number of bit planes used 000 only a background color 001 1 bit plane PLANE 1 010 2 bit planes PLANES...

Page 95: ...de Bits 1 0 not used DDFSTOP Data fetch Stop Ending position for data fetch Bits 15 8 not used Bits 7 2 pixel position H8 H3 Bit H3 only respected in HiRes Mode Bits 1 0 not used BPLxPTH Bit plane Poi...

Page 96: ...OF COLOR SELECTION This section contains summaries of playfield color selection including color register contents example colors and the differences in color selection in high resolution and low resol...

Page 97: ...F Bright blue FB0 Golden orange 06D Dark blue FD0 Cadmium yellow 91F Purple FF0 Lemon yellow ClF Violet BF0 Lime green FlF Magenta 8E0 Light green FAC Pink 0F0 Green DB9 Tan 2C0 Dark green C80 Brown 0...

Page 98: ...6 00111 0111 111 7 Playfield 2 Bit planes 6 4 2 01000 1000 000 8 01001 1001 001 9 01010 1010 010 10 01011 1011 011 11 01100 1100 100 12 01101 1101 101 13 01110 1110 110 14 01111 1111 111 15 10000 16 1...

Page 99: ...lane 5 Result 0 0 Normal operation use color register itself 0 1 Hold green and red B Bit plane 4 1 contents 0 Hold green and blue R Bit plane 4 1 contents Hold blue and red G Bit plane 4 1 contents C...

Page 100: ...Bit planes 3 1 0000 00 0 0001 01 1 0010 10 2 0011 11 3 0100 4 0101 NOT USED 5 0110 IN THIS MODE 6 0111 7 Playfield 2 Bit planes 4 2 1000 00 8 1001 01 9 1010 10 10 1011 11 11 1100 12 1101 NOT USED 13...

Page 101: ...92 Playfield Hardware...

Page 102: ...animation effects by using the blitter which is described in the chapter called Blitter Hardware Sprites are produced on screen by eight special purpose sprite DMA channels Basic sprites are 16 pixels...

Page 103: ...ata structure in memory You define a sprite by specifying its characteristics o On screen width of up to 16 pixels o Unlimited height o Any shape o A combination of three colors plus transparent o Any...

Page 104: ...pixels long Larger or smaller windows can be defined as required but it is recommended that you read the Playfield Hardware chapter before attempting to do so A larger area is actually scanned by the...

Page 105: ...0 to line 262 for the topmost edge of the sprite In the examples in this chapter an NTSC window with vertical positions from line 44 to line 243 is used This allows the normal display height of 200 l...

Page 106: ...reen s height or 1 256 of a PAL screen s height This pixel size corresponds to the low resolution and non interlaced modes of the normal full size playfield Sprites however are independent of playfiel...

Page 107: ...of the sprite Whenever the shape is narrower than the sprite you can control which part of the sprite is used to define the shape This particular shape could also start at any of the pixels from 2 7 i...

Page 108: ...that particular sprite DMA channel The eight sprites use system color registers 16 31 For purposes of color selection the eight sprites are organized into pairs and each pair uses four of the color r...

Page 109: ...__ Unused 28 00 _________________________ Sprite 6 or 7 01 _________________________ 10 _________________________ __ 11 _________________________ 31 Figure 4 6 Color Register Assignments If you requi...

Page 110: ...words contain position and control information and some contain color descriptions To create a sprite s data structure you need to o Write the horizontal and vertical position of the sprite into the f...

Page 111: ...criptor high word Color bits for line 2 End of data words Two words indicating the next usage of this sprite All memory addresses for sprites are word addresses You will need enough contiguous memory...

Page 112: ...e 1 N _________________________________ _ Pairs of words G _____ containing color _____ Data describing central information for A _____ lines of this sprite pixel lines D _____________________________...

Page 113: ...SPRxCTL Bits 15 8 The low eight bits of VSTOP Bit 7 Used in attachment Bits 6 3 Unused make zero Bit 2 The VSTART high bit Bit 1 The VSTOP high bit Bit 0 The HSTART low bit The value VSTOP VSTART def...

Page 114: ...ine becomes the color descriptor high word In this fashion you translate each line in the sprite into binary 0s and 1s See Figure 4 7 Each of the binary numbers formed by the combination of the two da...

Page 115: ...c mode In this mode once the sprite DMA channel begins to retrieve and display the data the display continues until the VSTOP position is reached Manual mode is described later on in this chapter The...

Page 116: ...e 0 pointer These pointers are dynamic they are incremented by the sprite DMA channel to point first to the control words then to the data words and finally to the end of data words After reading in t...

Page 117: ...ters MOVE W 0008 COLOR00 a0 Background color dark blue MOVE W 0000 COLOR01 a0 Foreground color black MOVE W 0FF0 COLOR17 a0 Color 17 yellow MOVE W 00FF COLOR18 a0 Color 18 cyan MOVE W 0FOF COLORl9 a0...

Page 118: ...BPL1PTL 1000 DC W SPR0PTH 0002 Sprite 0 pointer 25000 DC W SPR0PTL 5000 DC W SPR1PTH 0003 Sprite 1 pointer 30000 DC W SPR1PTL 0000 DC W SPR2PTH 0003 Sprite 2 pointer 30000 DC W SPR2PTL 0000 DC W SPR3...

Page 119: ...detect these collisions and exploit this capability for special effects In addition you can use collision detection to keep a moving object within specified on screen boundaries Collision Detection i...

Page 120: ...TOP to sprite BRA VLOOP Loop forever CREATING ADDITIONAL SPRITES To use additional sprites you must create a data structure for each one and arrange the display as shown in the previous section naming...

Page 121: ...en you may need to take into consideration their relative video priority that is which sprite appears in front of or behind another Each sprite has a fixed video priority with respect to all the other...

Page 122: ...9 Figure 4 9 Typical Example of Sprite Reuse In single sprite usage two all zero words are placed at the end of the data structure to stop the DMA channel from retrieving any more data for that partic...

Page 123: ...____________________________ word must be at ________________________________ least one video _________ line below actual _________ end of preceding _________ usage ________________________________ V...

Page 124: ...3FFC 0000 DC W 0FF0 0000 DC W 03C0 0000 DC W 0180 0000 DC W 0000 0000 End of sprite data OVERLAPPED SPRITES For more complex or larger moving objects you can overlap sprites Overlapping simply mean th...

Page 125: ...hed You can create a wider sprite display by placing two sprites next to each other For instance Figure 4 12 shows the spaceship sprite and how it can be made twice as large by using two sprites place...

Page 126: ...prite creating two sprites of the same size and located at the same position o Set a bit called ATTACH in the second sprite control word The fifteen colors are selected from the full range of color re...

Page 127: ...e of Spaceship Sprite PIXEL NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Line 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Line 2 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Line 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Line 4 0 0...

Page 128: ...1 in the data structure for the odd numbered sprite So in this example you set bit 7 in sprite control word 2 in the data structure for sprite 1 When the sprites are moved the Copper list must keep t...

Page 129: ...ite that is showing a DMA controlled icon near the top of the screen can also be reloaded manually to show a vertical colored bar near the bottom of the screen Sprites can be activated manually even w...

Page 130: ...ry The shifting and data output does not begin again until the next time this converter is loaded from the data registers Because the video image is produced by an electron beam that is being swept fr...

Page 131: ..._ Parallel to Sprite serial __ __ serial converter video data ___ _________________ _ _________________ Output to Parallel to video priority serial converter logic _________________ _____ ____________...

Page 132: ...lue part of SPRxPOS When these values match the system enables the sprite data access The sprite DMA channel examines the contents of VSTOP from SPRxCTL which is the location of the line after the las...

Page 133: ...splay progresses Therefore pointer registers must be freshly written during the start of the vertical blanking period SPR0PTH and SPR0PTL This pair of registers contains the 32 bit word address of Spr...

Page 134: ...position for a sprite image bits V7 V0 o Bit 7 is the attach bit This bit is valid only for odd numbered sprites It indicates that sprites 0 1 or 2 3 or 4 5 or 6 7 will for color interpretation be co...

Page 135: ...TA SPR1DATB data registers for Sprite 1 SPR2DATA SPR2DATB data registers for Sprite 2 SPR3DATA SPR3DATB data registers for Sprite 3 SPR4DATA SPR4DATB data registers for Sprite 4 SPR5DATA SPR5DATB data...

Page 136: ...ed 01 17 10 18 11 19 2 or 3 00 Not used 01 21 10 22 11 23 4 or 5 00 Not used 01 25 10 26 11 27 6 or 7 00 Not used 01 29 10 30 11 31 Selects transparent mode If the bit combinations from attached sprit...

Page 137: ...3 1000 24 1001 25 1010 26 1011 27 1100 28 1101 29 1110 30 1111 31 INTERACTIONS AMONG SPRITES AND OTHER OBJECTS Playfields share the display with sprites Chapter 7 System Control Hardware shows how pla...

Page 138: ...shows you how to directly access the audio hardware to produce sounds The major topics in this chapter are o A brief overview of how a computer produces sound o How to produce simple steady and changi...

Page 139: ...licators of Microprocessors Rochelle Park New Jersey Hayden 1980 INTRODUCING SOUND GENERATION Sound travels through air to your ear drums as a repeated cycle of air pressure variations or sound waves...

Page 140: ...as high as that of the first tone and its perceived pitch is twice as high The second parameter that defines a waveform is its amplitude In an electronic circuit amplitude relates to the voltage or cu...

Page 141: ...s the voltage waveforms to a loudspeaker which translates them into air pressure vibrations that the listener perceives as sound A computer cannot store analog waveform information In computer product...

Page 142: ...00 0 11 39 100 20 12 75 100 40 13 103 100 60 14 121 100 80 15 127 100 100 16 121 100 80 17 103 100 60 18 75 100 40 19 39 100 20 THE AMIGA SOUND HARDWARE The Amiga has four hardware sound channels You...

Page 143: ...the waveform and create the sample Table in memory 3 Set registers telling the system where to find the data and the length of the data 4 Select the volume at which the tone is to be played 5 Select...

Page 144: ...it reads as two bytes of data To use audio channel 0 write the address of audiodata into AUD0LC where the audio data is organized as shown below For simplicity AUDxLC in the Table below stands for the...

Page 145: ...e location registers WHERE0DATA LEA CUSTOM a0 Base chip address LEA AUDIODATA a1 MOVE L a1 AUDOLCH a0 Put address 32 bits into location register The length of the data is the number of samples in your...

Page 146: ...by the waveform depends upon its frequency To tell the system what frequency to use you need to specify the sampling period The sampling period specifies the number of system clock ticks or timing in...

Page 147: ...ck constant Period value clock interval samples per second Thus the minimum period value is derived by dividing 34 642 microseconds per sample by the number of microseconds per interval 34 642 microse...

Page 148: ...G THE PERIOD VALUE After you have selected the desired interval between data samples you can calculate the value to place in the period register by using the period formula desired interval clock cons...

Page 149: ...e high quality sound avoiding aliasing distortion you should observe the limitations on period values that are discussed in the section below called Producing Quality Sound For the relationship betwee...

Page 150: ...he audio channel as shown below BEGINCHAN0 LEA CUSTOM a0 MOVE W DMAF_SETCLR DMAF_AUD0 DMAF_MASTER DMACON a0 STOPPING THE AUDIO DMA You can stop the channel by writing a 0 into the AUDxEN bit at any ti...

Page 151: ...AEN along with a 1 in the SET CLR bit and a 1 in the position of the AUDxEN bit of the channel or channels you want to start EXAMPLE In this example which gathers together all of the program segments...

Page 152: ...nnel then stores the values in back up registers Once the original registers have been read by the DMA channel you can change their values without disturbing the operation you started with the origina...

Page 153: ...as its interaction with the audio DMA system The example assumes that the period volume and length of the data set remains the same for the sine wave and the triangle wave INTERRUPT PROGRAM If wave t...

Page 154: ...ulate a channel s frequency or amplitude or do both types of modulation on a channel at the same time Amplitude modulation affects the volume of the waveform It is often used to produce vibrato or tre...

Page 155: ...frequency of channel 1 you set two attach bits bit 0 to modulate the volume and bit 4 to modulate the period When period and volume are both modulated words in the modulator channel s data set are def...

Page 156: ...attach channel 3 Writing a 1 into channel 3 s modulate bits only disables its audio output Table 5 5 Channel Attachment for Modulation ADKCON REGISTER Bit Name Function 7 ATPER3 Use audio channel 3 t...

Page 157: ...can avoid thumps by arranging the average amplitude of each wave to be about the same value The average amplitude is the sum of the bytes in the waveform divided by the number of bytes in the wavefor...

Page 158: ...ere is only one waveform buffer the hardware automatically resets the pointers so no software overhead is used for resetting them The Joining Tones section illustrated how you could join ends of tones...

Page 159: ...nal Proportionally the digital value used to represent the waveform amplitude will have a lower error As you increase the number of possible sample levels you decrease the relative size of each step a...

Page 160: ...e of the filter as shown in these calculations 12 4 16KHz 12 4 8KHz Filter response 12 KHz sampling frequency 0 db ____ Diff Sum 4 30 db ____ __ _ ___ _____ _____________________ 05 10 15 20 25 30 KHz...

Page 161: ...ou may be producing a complex waveform with multiple frequency elements rather than a pure sine wave LOW PASS FILTER The system includes a low pass filter that eliminates aliasing distortion as descri...

Page 162: ...ossible to create sound by writing audio data one word at a time to the audio output addresses instead of setting up a list of audio data in memory This method of controlling the output is more proces...

Page 163: ...G 1568 0 1564 5 1572 2 135 133 G 1661 2 1657 2 1666 8 The Table above shows the period values to use with a 16 byte sample to make tones in the second octave above middle C To generate the tones in th...

Page 164: ...5 7 were generated using the formula shown below To calculate the tone generated with a given sample size and period use Clock Constant 3579545 Frequency 880 8hz Sample Bytes Period 16 Period The clo...

Page 165: ...26 224 B 123 47 123 74 123 70 214 212 C 130 81 130 68 130 71 202 200 C 138 59 138 44 138 55 190 189 D 146 83 147 18 146 61 180 178 D 155 56 155 36 155 67 170 168 E 164 81 164 50 164 94 160 159 F 174 6...

Page 166: ...99 13 697 11 151 150 F 739 99 740 80 738 94 143 141 G 783 99 782 24 786 10 135 133 G 830 61 828 60 833 39 Sample size 32 bytes AUDxLEN 16 254 252 A 880 0 880 8 879 7 240 238 A 932 3 932 2 931 4 226 22...

Page 167: ...66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 128 BYTE SAMPLE 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112...

Page 168: ...61 0 4 129 6 9 60 0 6 28 7 2 59 0 7 27 7 5 58 0 9 26 7 8 57 1 0 25 8 2 56 1 2 24 8 5 55 1 3 23 8 9 54 1 5 22 9 3 53 1 6 21 9 7 52 1 8 20 10 1 51 2 0 19 10 5 50 2 1 18 11 0 49 2 3 17 11 5 48 2 5 16 12...

Page 169: ...arrives state 010 is entered and the main loop continues until the DMA is turned off The length counter counts down once with each word that comes in When it finishes a DMA restart request goes to Ag...

Page 170: ...able percntrld Reload period counter from back up latch typically written by processor with AUDxPER can also be written by attach mode percount Count period counter down one latch perfin Period counte...

Page 171: ...UDxAV AUDxAP AUDxAV no attach stuff or else attach volume Condition for normal DMA and interrupt requests sq2 1 0 The name of the state flip flops MSB to LSB Figure 5 8 Audio State Diagram 162 Audio H...

Page 172: ...t four megabytes per second It can draw lines at almost a million pixels per second In block move mode the blitter can perform any logical operation on up to three source areas it can shift up to two...

Page 173: ...C and one destination channel called D Each of these channels has separate address pointer modulo and data registers and an enable bit Two have shift registers and one has a first and last word mask r...

Page 174: ...d 16 pixels of a single bitplane If this image required sixteen colors four bit planes like this would be required in memory and four copy move operations would be required to completely move the imag...

Page 175: ...el is added to the address pointer A row is defined by the width stored in BLTSIZE NOTE The modulo values are in bytes not words Since the blitter can only operate on words the least significant bit i...

Page 176: ...ather than rectangular regions by setting the horizontal or vertical count in BLTSIZE to 1 Because each DMA channel has its own modulo register data can be moved among bitplanes of different widths Th...

Page 177: ...and the possible values for a single bit from each one A B C D BLTCON0 position MINTERM ___ 0 0 0 0 ABC __ 0 0 1 1 ABC _ _ 0 1 0 2 ABC _ 0 1 1 3 ABC __ 1 0 0 4 ABC _ 1 0 1 5 ABC _ 1 1 0 6 ABC 1 1 1 7...

Page 178: ...has a higher precedence so AB BC is equal to AB BC Any function can be written as a sum of minterms If we wanted to calculate the function where D is one when the A bit is set and the C bit _ is clear...

Page 179: ...h the car mask the B DMA channel to fetch the actual car data the C DMA channel to fetch the background and the D DMA channel to write out the new image NOTE We must fetch the destination background b...

Page 180: ...C0 _ _ D A 0F D AB 30 _ D B CC D AB 0C _ __ D B 33 D AB 03 D C AA D BC 88 _ _ D C 55 D BC 44 _ D AC A0 D BC 22 _ __ D AC 50 D AC 11 _ _ D AC 0A D A B F3 __ _ _ D AC 05 D A B 3F _ D A B FC D A C FS _...

Page 181: ...erms 7 6 5 and 4 When written as a set of 1s for the selected minterms and 0s for those not selected the value becomes Minterm Number 7 6 5 4 3 2 1 0 Selected Minterms 1 1 1 1 0 0 0 0 F 0 equals F0 2...

Page 182: ...shifting operation is completely free it requires no more time to execute a blit with shifts than a blit without shifts as opposed to shifting with the 68000 The shift is normally towards the right Th...

Page 183: ...irst and last word masks When not in use both should be initialized to all ones FFFF NOTE Text fonts on the Amiga are stored in a packed bit map Individual characters from the font are extracted using...

Page 184: ...___ Source is passed through mask when it is a one otherwise the destination is copied Destination does not change where mask is 0 Figure 6 4 Extracting a Range of Columns To do this we point the B DM...

Page 185: ...down towards increasing addresses however we run into a problem we overwrite the second row before we get a chance to copy it The blitter has a special mode of operation descending mode that solves th...

Page 186: ...ion are as follows 1 Use the A DMA channel disabled preloaded with all ones and the appropriate mask and shift values to mask the cookie cut function Use the B channel to fetch the source data the C c...

Page 187: ...ILL MODE In addition to copying data the blitter can simultaneously perform a fill operation during the copy The fill operation has only one restriction the area to fill must be defined first by drawi...

Page 188: ...e FCI Bit Bit Is a 0 If the FCI bit is a 1 instead of a 0 the area outside the lines is filled with ls and the area inside the lines is left with 0s in between BEFORE AFTER ____________________ ______...

Page 189: ...nt the filling stops BLITTER DONE FLAG When the BLTSIZE register is written the blit is started The processor does not stop while the blitter is working though they can both work concurrently and this...

Page 190: ...t even the first time Use of the ROM kernel function WaitBlit is recommended You should also check the blitter done flag before using results of a blit The blit may not be finished so the data may not...

Page 191: ...blitter is pipelined This means that rather than performing all of the above operations in one blitter cycle the operations are spread over two blitter cycles Here cycle is used very loosely for simp...

Page 192: ...l o No competing bus activity o Three word blit o Typical operation involves fetching all sources twice before the first destination becomes available This is due to internal pipelining Care must be t...

Page 193: ...riptions of the use of these registers and control bits in line drawing mode In line mode the blitter draws a line from one point to another which can be viewed as a vector The direction of the vector...

Page 194: ...culations have the effect of normalizing our line into octant 0 since we have already informed the blitter of the real octant to use it has no difficulty drawing the line We initialize the A pointer r...

Page 195: ...o draw the line using exclusive or mode so it can be easily erased by drawing it again the function ABC AC can be used We set the blit height to the length of the line which is dx 1 The width must be...

Page 196: ...DE 1 BLTCON1 bit OVFLAG 0 BLTCON1 bits 4 2 octant number from Table BLTCON1 bits 15 12 start bit for line texture 0 last significant bit if 4 dy 2 dx 0 then BLTCON1 bit SIGNFLAG 1 else BLTCON1 bit SIG...

Page 197: ...ht ticks The system clock speed for NTSC Amiga s is 7 16 megahertz PAL Amiga s 7 09 megahertz The clock for the blitter is the system clock To calculate the total time for the blit in microseconds exc...

Page 198: ...use missed DMA cycles can cause lost data noise in the sound output or on screen interruptions The Copper has the next priority because it has to perform its operations at the same time during each di...

Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...

Page 200: ...nstruction TAS should never be used in the Amiga the indivisible read modify write cycle that is used only in this instruction will not fit into a DMA memory access slot Average 68000 cycle internal m...

Page 201: ...l blanking T TIMING CYCLE T 7 4 2 3 1 4 2 3 1 Figure 6 12 Time Slots Used by a High Resolution Display Each horizontal line in a normal full sized display contains 320 pixels in low resolution mode or...

Page 202: ...the blitter It does not cover the line drawing hardware o The upper left comer shows how the first and last word masks are applied to the incoming A source data When the blit shrinks to one word wide...

Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...

Page 204: ...ts to the right o In descending mode the blitter decrements the pointers subtracts the modules and shifts to the left o Area fill only works correctly in descending mode o Check BLTDONE before writing...

Page 205: ...es move w DEST BLTCON0 a1 only enable destination First we deal with the smaller blits moveq 3f d1 Mask out mod 64 words and w d0 d1 beq dorest none good do one blit sub l d1 d0 otherwise remove remai...

Page 206: ...if y x octant is 2 moveq l OCTANT1 LINEMODE d5 otherwise octant is 1 bra lineagain go to the common section ygtx exg d2 d3 X must be greater than Y moveq l OCTANT2 LINEMODE d5 we are in octant 2 bra...

Page 207: ...and add 1 to height 2 to width btst DMAB_BLTDONE 8 DMACONR al safety check waitblit btst DMAB_BLTDONE 8 DMACONR a1 wait for blitter bne waitblit move w d3 BLTBMOD a1 B mod 4 Y sub w d2 d3 ext l d3 mov...

Page 208: ...ess the custom registers tst d0 if no words just return beq gone lea DMACONR a2 a3 get the address of dmaconr moveq l DMAB BLTDONE 8 d2 get the bit number BLTDONE btst d2 a3 check to see if we re done...

Page 209: ...st d2 a3 Check blit done wait2 btst d2 a3 Check again bne wait2 oops not ready loop around inloop move w d3 a4 stuff new word to make vertical move w d1 a5 start the blit subq w 1 d0 is that the last...

Page 210: ...DUCTION This chapter covers the control hardware of the Amiga system including the following topics o How playfield priorities may be specified relative to the sprites o How collisions between objects...

Page 211: ...ty may be changed relative to sprites FIXED SPRITE PRIORITIES You cannot change the relative priorities of the sprites They will always appear on the screen with the lower numbered sprites appearing i...

Page 212: ...your hands represent the four pairs of sprites and two fingers of your other hand represent the two playfields Just as you cannot change the sequence of the four fingers on the one hand neither can yo...

Page 213: ...E PRIORITY CONTROL REGISTER This register lets you define how objects will pass in front of each other or hide behind each other Normally playfield 1 appears in front of playfield 2 The PF2PRI bit rev...

Page 214: ...een Here is a sample of possible BPLCON2 register contents that would create something a little unusual BITS 15 7 PF2PRI PF2P2 0 PF1P2 0 VALUE 0s 1 010 000 This will result in a sprite playfield prior...

Page 215: ...verything is displayed together sprite 0 is more important than playfield 2 but less important 3883 than playfield 1 So even though you can t see the boundary the sprite disappears behind the invisibl...

Page 216: ...ve using the blitter This is called playfield animation If one playfield is defined as the backdrop or playing area and the other playfield is used to define objects in addition to the sprites you can...

Page 217: ...sprite 0 or l 4 Odd bit planes to sprite 6 or 7 3 Odd bit planes to sprite 4 or 5 2 Odd bit planes to sprite 2 or 3 1 Odd bit planes to sprite 0 or 1 0 Even bit planes to odd bit planes NOTE The numb...

Page 218: ...t plane 5 collision 3 MVBP4 Match value for bit plane 4 collision 2 MVBP3 Match value for bit plane 3 collision 1 MVBP2 Match value for bit plane 2 collision 0 MVBP1 Match value for bit plane 1 collis...

Page 219: ...operations based on the beam position NOTE The Copper is already capable of watching the display position for you and doing certain register based operations automatically Refer to Copper Interrupts...

Page 220: ...osition bits V7 V0 Bits 7 0 The horizontal position bits H8 H1 Horizontal resolution is 1 160th of the screen width VPOSW Write only Bits same as VPOSR above VHPOSW Write only Bits same as VHPOSR abov...

Page 221: ...1 have been routed to the expansion connector for use by external hardware for interrupts These are known as the external low and external high level interrupts These interrupt lines are connected to...

Page 222: ...gisters and how you use them SET AND CLEAR The interrupt registers as well as the DMA control register use a special way of selecting which of the bits are to be set or cleared Bit 15 of these registe...

Page 223: ...required to perform many different tasks during the vertical blanking interval Among these tasks are the updating of various pointer registers rewriting lists of Copper tasks when necessary and other...

Page 224: ...1 and 0 respectively This level 4 interrupt signals audio block done When the audio DMA is operating in automatic mode this interrupt occurs when the last word in an audio data stream has been access...

Page 225: ...t 0 TBE for transmit buffer empty specifies that the output buffer of the UART needs more data and data can now be written into this buffer This bit generates a level 1 interrupt Hardware Exec Softwar...

Page 226: ...ntrol read only DMACON Direct Memory Access Control write only The contents of this register are shown in Table 7 5 bit on if enabled PROCESSOR ACCESS TO CHIP MEMORY The Amiga chips access chip memory...

Page 227: ...al priority over the 68000 9 DMAEN DMA enable This is a master DMA enable bit It enables the DMA for all of the channels at bits 8 0 8 BPLEN Bit plane DMA enable 7 COPEN Coprocessor DMA enable 6 BLTEN...

Page 228: ...he 68000 RESET instruction works much like external reset or power on All memory and AUTOCONFIGTM cards disappear and the ROM image appears at location 00000000 The difference is that the CPU continue...

Page 229: ...220 System Control Hardware...

Page 230: ...s the interface hardware through which the Amiga talks to the outside world including the following features o Two multiple purpose mouse joystick light pen control ports o Disk controller for floppy...

Page 231: ...tors RGB monochrome Nl SC RF modulator video slot CONTROLLER PORT INTERFACE Each Amiga has two nine pin connectors that can be used for input or output with many different kinds of controllers The Fig...

Page 232: ...so be conFigured as outputs These buttons are optional REGISTERS USED WITH THE CONTROLLER PORT JOY0DAT DFF00A Counter for digital mouse input port 1 JOY1DAT DFF00C Counter for digital mouse input port...

Page 233: ...decrement when the mouse is moved to the left or up away from you MOUSE QUADRATURE V VQ D1 D0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 Case 1 Count up ________ ________ ________ ____ V ____ ________ ________...

Page 234: ...irection Vertical blanking happens once each 1 60th of a second If you read the mouse once each vertical blanking period you will most likely find a count difference from the previous count of less th...

Page 235: ...t 1 is connected to bit 6 port 2 is connected to bit 7 See the 8520 Appendix for more information A logic state of 1 means switch open A logic state of 0 means switch closed o Button 2 right button on...

Page 236: ...ret the data once you have read it from these registers The true logic state of the switch data in these registers is 1 switch closed _________________ This is the 1 2 3 4 5 way the pins 6 7 8 9 are n...

Page 237: ...if the function the button controls is duplicated via the keyboard or another mechanism This button may be read in the same manner as the right mouse button READING PROPORTIONAL CONTROLLERS Each of th...

Page 238: ...interval During vertical blanking you write a value into an address called POTGO For a standard X Y joystick this value is hex 0001 Writing to this register starts the operation of some special hardw...

Page 239: ...r cannot overflow within the span of a single screen This allows you to know for certain whether an overflow is indicated by the controller PROPORTIONAL CONTROLLER REGISTERS The following registers ar...

Page 240: ...al input readings will need to be averaged Port 1 connector ___________________ ________________________ o o o o o POT1Y POT1X POT1DAT o o o o COUNTER COUNTER DFF014 __________ _ ____________ ________...

Page 241: ...light pen operation are as follows 1 Just as the system exits vertical blank the capture circuitry for the light pen is automatically enabled 2 The video beam starts to create the picture sweeping fro...

Page 242: ...readings together To enable the light pen input write a 1 into bit 3 of BPLCON0 Once the light pen input is enabled and the light pen issues a trigger signal the value in VPOSR is frozen If no trigge...

Page 243: ...OLLER PORT The Amiga can read and interpret many different and nonstandard controllers The control lines built into the POTGO register address DFF034 can redefine the functions of some of the controll...

Page 244: ...his set the proper pin to output and drive the line high set both OUT and DAT to 1 Reading POTINP will produce a 0 if the button is pressed a 1 if it is not The joystick fire buttons can also be confi...

Page 245: ...ing CIABPRB BFD100 eight output bits for disk selection control and stepping ADKCON DFF09E control bits write only register ADKCONR DFF010 control bits read only register DSKPTH DFF020 DMA pointer 32...

Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...

Page 247: ...rds when this signal is active Some drives will refuse to step others will attempt the step possibly causing alignment damage All new drives must refuse to step outward in this condition PA3 DSKPROT D...

Page 248: ...is at the outside of the disk This line must be set up before the actual step pulse with a separate write to the register PB0 DSKSTEP Step the heads of the disk This signal must always be used as a q...

Page 249: ...e address from which or to which the data is to be transferred The lowest bit of the address must be zero and the buffer must be in CHIP memory The value must be written as a single long word to the D...

Page 250: ...counts down to 0 the transfer stops The recommended method of reading from the disk is to read an entire track into a buffer and then search for the sector s that you want Using the DSKSYNC register...

Page 251: ...various DMA bits must be true This means the DMAEN bit in DKSLEN and the DSKEN DMAEN bits in DMACON 13 DISKWRITE The disk write bit in DSKLEN is enabled 12 WORDEQUAL Indicates the DISKSYNC register eq...

Page 252: ...40 ns Value of 10 selects 280 ns Value of 11 selects 560 ns 12 MFMPREC Value of 0 selects GCR Precompensation Value of 1 selects MFM Precompensation 10 WORDSYNC Value of 1 enables synchronizing and st...

Page 253: ...YNC bit is enabled in ADKCON no data is transferred until a word is found in the input stream that matches the word in the DSKSYNC register On read DMA will start with the following word from the disk...

Page 254: ...1 microsecond handshake pulse the pulse must be at least 85 microseconds for operation with all models of Amiga keyboards If another keystroke is received before the previous one has been accepted by...

Page 255: ...ave two more keys that are cut out of larger keys on the USA version These are 30 cut out from the left shift and 2B cut out from the return key RAW KEYCODES 40 5F HEX CODES COMMON TO ALL KEYBOARDS 40...

Page 256: ...key switch at each intersection see Appendix H for a diagram of the matrix Because of this the keyboard is subject to a phenomenon called phantom keystrokes While this is generally not a problem for...

Page 257: ...bed are pressed Normally the keyboard will appear to have N key rollover which means that you will run out of fingers before generating a ghost character NOTE Seven keys are not part of the matrix and...

Page 258: ...Figure 8 9 The Amiga 1000 Keyboard Showing Keycodes in hex Figure 8 10 the Amiga 500 2000 Keyboard showing Keycodes in hex Interface Hardware 249...

Page 259: ...UCTION TO SERIAL CIRCUITRY The Paula custom chip contains a Universal Asynchronous Receiver Transmitter or UART This UART is programmable for any rate from 110 to over 1 000 000 bits per second It can...

Page 260: ...ight or nine this allows for 8 bit transmission with parity In either case the receive circuitry expects to see one start bit eight or nine data bits and at least one stop bit Receive mode is set by b...

Page 261: ...T BUFFER EMPTY Not a mirror interrupt occurs when the buffer becomes empty When bit 14 is a 1 the data in the output data register SERDAT has been transferred to the serial output shift register so SE...

Page 262: ...ite the data into this register the system will begin the transmission at the baud rate you selected At the start of the operation this data is transferred from SERDAT into an internal serial shift re...

Page 263: ...ster stops shifting and signals shift register empty TSRE when there is a 1 bit present in the bit shifted out position and the rest of the contents of the shift register are 0s When new nonzero conte...

Page 264: ...p the 16 combinations to 16 arbitrary colors Note that the sync signals from the Amiga are unbuffered For use with any device that presents a heavy load on the sync outputs external buffers will be re...

Page 265: ...256 Interface Hardware...

Page 266: ...APPENDIX A REGISTER SUMMARY ALPHABETICAL ORDER This appendix contains the definitive summary in alphabetical order of the register set and the uses of the individual bits Appendix A 257...

Page 267: ...ing a read only register will cause unexpected results All of the pointer type registers are organized as 32 bits on a long word boundary These registers may be written with one MOVE L instruction The...

Page 268: ...2 Use audio channel 1 to modulate period of channel 2 04 USE0P1 Use audio channel 0 to modulate period of channel 1 03 USE3VN Use audio channel 3 to modulate nothing 02 USE2V3 Use audio channel 2 to m...

Page 269: ...ans that the smallest number that should be placed in this register is 124 decimal This corresponds to a maximum sample frequency of 28 86 kHz AUDxVOL 0A8 W P Audio channel x volume This register cont...

Page 270: ...X 10 USEB X 09 USEC X 08 USED X 07 LF7 X 06 LF6 X 05 LF5 X 04 LF4 EFE 03 LF3 IFE 02 LF2 FCI 01 LF1 DESC 00 LF0 LINE 0 ASH 3 0 Shift value of A source BSH 3 0 Shift value of B source USEA Mode control...

Page 271: ...single bit true 8000 most bits LINE DRAW will pass the C field unchanged LINE DRAW not A and C hut one bit will LINE DRAW invert the C field and combine it LINE DRAW with texture A and B and not C LIN...

Page 272: ...5 h4 h3 h2 h1 h0 w5 w4 w3 w2 w1 w0 h height vertical lines 10 bits 1024 lines max w width horizontal pixels 6 bits 64 words 1024 pixels max LINE DRAW BLTSIZE controls the line length and starts LINE D...

Page 273: ...low 15 bits This pair of registers contains the 18 bit address of blitter source x A B C or destination x D DMA data This pointer must be preloaded with the starting address of the data to be processe...

Page 274: ...1P1 00 X PF1H0 PF1lP0 HIRES High resolution 640 mode BPU Bit plane use code 000 110 NONE through 6 inclusive HOMOD Hold and modify mode DBLPF Double playfield PF1 odd PF2 even bit planes COLOR Composi...

Page 275: ...state if included It also controls the individual inclusion of odd numbered sprites in the collision detection by logically OR ing them with their corresponding even numbered sprite BIT FUNCTION DESC...

Page 276: ...to sprite 2 or 3 01 Playfield 1 to sprite 0 or 1 00 Playfield 1 to playfield 2 COLORxx 180 W D Color Table xx There are 32 of these registers xx 00 31 and they are sometimes collectively called the co...

Page 277: ...is is a dummy address that is generated by the Copper whenever it is loading instructions into its own instruction register This actually occurs every Copper cycle except for the second IR2 cycle of t...

Page 278: ...omparison bit VE Enable comparison mask bit HE Enable comparison mask bit NOTE BFD Blitter finished disable When this bit is true the Blitter Finished flag will have no effect on the Copper When this...

Page 279: ...me It is important that one of the jump registers be initialized and its jump strobe address hit after power up but before Copper DMA is initialized This insures a determined startup address and state...

Page 280: ...TRT left edge of display data fetch PURPOSE H8 H7 H6 H5 H4 Extra wide max 0 0 1 0 1 Wide 0 0 1 1 0 Normal 0 0 1 1 1 Narrow 0 1 0 0 0 DDFSTOP right edge of display data fetch PURPOSE H8 H7 H6 H5 H4 Nar...

Page 281: ...e all DMA below 08 BPLEN Bit plane DMA enable 07 COPEN Copper DMA enable 06 BLTEN Blitter DMA enable 05 SPREN Sprite DMA enable 04 DSKEN Disk DMA enable 03 AUD3EN Audio channel 3 DMA enable 02 AUD2EN...

Page 282: ...SKLEN 024 W P Disk length This register contains the length number of words of disk DMA data It also contains two control bits a DMA enable bit and a DMA direction read write bit BIT FUNCTION DESRIPTI...

Page 283: ...ck finished 07 AUD0 4 Audio channel 0 block finished 06 BLIT 3 Blitter finished 05 VERTB 3 Start of vertical blank 04 COPER 3 Copper 03 PORTS 2 I O ports and timers 02 SOFT 1 Reserved for software ini...

Page 284: ...d multiplexed into the DENISE chip during the clock times shown in the Table This Table is for reference only and should not be needed by the programmer Note that the joystick functions are all active...

Page 285: ...NECTORS PAULA Loc Dir Sym Pin Pin Pin Name RIGHT Y RY 9 36 POT1Y RIGHT X RX 5 35 POT1X LEFT Y LY 9 33 POT0Y LEFT X LX 5 32 POT0X POTGO 034 W P Pot port data write and start POTGOR 016 R P Pot port dat...

Page 286: ...ffer This address reads data from a receive data buffer Data in this buffer is loaded from a receiving shift register whenever it is full Several interrupt request bits are also read at this address a...

Page 287: ...e Low bit SH0 is in SPRxCTL register below SPRxCTL register writing this address disables sprite horizontal comparator circuit BIT SYM FUNCTION 15 08 EV7 EV0 End stop vertical value low 8 bits 07 ATT...

Page 288: ...cond refresh time slot of every other line to identify lines with long counts 228 There are four refresh time slots and any not used for strobes will leave a null FF address on the destination address...

Page 289: ...280 Appendix A...

Page 290: ...APPENDIX B REGISTER SUMMARY ADDRESS ORDER This appendix contains information about the register set in address order Appendix B 281...

Page 291: ...nation address bus S Strobe write address with no register bits Writing the register causes the effect PTL PTH Chip memory pointer that addresses DMA data Must be reloaded by a processor before use ve...

Page 292: ...SERPER 032 W P Serial port period and control POTGO 034 W P Pot port data write and start JOYTEST 036 W D Write to all 4 joystick mouse counters at once STREQU 038 S D Strobe for horiz sync with VB a...

Page 293: ...clear or set bits ADKCON 09E W P Audio disk UART control AUD0LCH 0AO W A Audio channel 0 location high 3 bits AUD0LCL 0A2 W A Audio channel 0 location low 15 bits AUD0LEN 0A4 W P Audio channel 0 lengt...

Page 294: ...bits BPL6PTL 0F6 W A Bit plane 6 pointer low 15 bits 0F8 0FA 0FC 0FE BPLCON0 100 W A D Bit plane control register misc control bits BPLCON1 102 W D Bit plane control reg scroll value PF1 PF2 BPLCON2...

Page 295: ...ge data register B SPR1POS 148 W A D Sprite 1 vert horiz start position data SPR1CTL 14A W A D Sprite 1 vert stop position and control data SPR1DATA 14C W D Sprite 1 image data register A SPR1DATB 14E...

Page 296: ...Table 06 COLOR07 18E W D Color Table 07 COLOR08 190 W D Color Table 08 COLOR09 192 W D Color Table 09 COLOR10 194 W D Color Table 10 COLORll 196 W D Color Table 11 COLOR12 198 W D Color Table 12 COLOR...

Page 297: ...288 Appendix B...

Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...

Page 299: ...posite sync O 40 HSY Horizontal sync I O 41 VSS Ground I 42 48 D15 D9 Data bus lines 15 to 9 I O DENISE PIN ASSIGNMENT PIN DESIGNATION FUNCTION DEFINITION 01 07 D6 D0 Data bus lines 6 to 0 I O 08 M1H...

Page 300: ...vel 3 I 18 INT6 Interrupt level 6 I 19 26 RGA8 RGA1 Register address bus 8 1 I 27 VCC 5 Volt I 28 CCK Color clock I 29 CCKQ Color clock delay I 30 AUDB Right audio O 31 AUDA Left audio O 32 POT0X Pot...

Page 301: ...r clock I 35 XCLR Alternate master clock I 36 XCLKEN Master clock enable I 37 CDAC Inverted shifted 7MHZ clk O 38 7MHZ 28MHZ clk divided by four O 39 CCRQ Color clock delay O 40 CCR Color clock O 41 T...

Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...

Page 303: ...GE NOTES 000000 03FFFF 256K Bytes of chip RAM 040000 07FFFF 256K bytes of chip RAM option card 080000 0FFFFF 512K Extended chip RAM to 1 MB 100000 1FFFFF Reserved Do not use 200000 9FFFFF Primary 8 MB...

Page 304: ...de timing or loading information The second part briefly describes the functions of those pins whose purpose may not be evident The third part contains a list of the connections for certain internal c...

Page 305: ...ccess in order to assure compatibility of their software with the system PART 1 OUTSIDE WORLD CONNECTORS This is a list of the connections to the outside world on the Amiga RS232 and MIDI Port A500 CB...

Page 306: ...lup AUTODXT 15 GND NC ERROR 16 GND RESET INIT 17 GND GND SLCT IN 18 22 GND GND GND 23 5 GND GND 24 NC GND GND 25 Reset GND GND KEYBOARD RJ11 A1000 A2000 1 5 Volts KCLK 2 CLOCK KDAT 3 DATA NC 4 GND GND...

Page 307: ...00 with A2000 differences noted 1 RDY 13 SIDEB 2 DKRD 14 WPRO 3 GND 15 TK0 4 GND 16 DKWEB 5 GND 17 DKWDB 6 GND 18 STEPB 7 GND 19 DIRB 8 MTRXD 20 SEL3B A2000 not used 1 9 SEL2B A2000 SEL3B 1 21 SEL1B A...

Page 308: ...8 D8 J D9 9 gnd K gnd 10 D7 L D6 11 5 M 5 12 D4 N D5 13 gnd P gnd 14 D3 R D2 15 5 S 5 16 D0 T D1 17 gnd U gnd 18 DRA4 V DRA3 19 DRA5 W DRA2 20 DRA6 X DRA1 21 DRA7 Y DRA0 22 gnd Z gnd 23 RAS AA RRW 24...

Page 309: ...Clock 16 x x x x C1 Clock 17 x x x x OVR 18 x x x x RDY 19 x x x x INT2 20 x PALOPE x x No Connect x BOSS 21 x x x x A5 22 x x x x INT6 23 x x x x A6 24 x x x x A4 25 x x x x ground 26 x x x x A3 27 x...

Page 310: ...x x x x DTACK 67 x x x x D13 68 x x x x R W 69 x x x x D12 70 x x x x LDS 71 x x x x D11 72 x x x x UDS 73 x x x x Ground 74 x x x x AS 75 x x x x D0 76 x x x x D10 77 x x x x D1 78 x x x x D9 79 x x...

Page 311: ...e See timing diagrams in the following section D0 I O Dl I O D2 I O D3 I O D0 D7 comprise an eight bit bidirectional bus D4 I O for communication with parallel devices D5 I O nominally a printer D6 I...

Page 312: ...wledge delay TS nsp x upc Acknowledge width nsp not specified upc under program control PARALLEL CONNECTOR INTERFACE TIMING INPUT CYCLE PA 7 0 _____ ____________________________________________ ____ P...

Page 313: ...to frame ground CD I y Carrier detect 5V n 50 ma maximum WARNING 5V AUDO O n Audio output from left channels 0 3 port intended to send audio to the modem AUDI I n Audio input to right channels 1 2 por...

Page 314: ...nterface to four types of devices 1 Mouse or trackball 3 buttons max 2 Digital joystick 2 button max 3 Proportional pot or proportional joystick 2 buttons max 4 Light pen including pen pressed to scre...

Page 315: ...can be resolved as follows Velocity Distance max SampleTime Velocity SQRT DeltaX 2 DeltaY 2 SampleTime For an Amiga with a 200 count per inch mouse sampling during each vertical blanking interval the...

Page 316: ...JOYSTICK INPUTS PIN MNEMONIC DESCRIPTION HARDWARE REGISTER NOTES 1 FORWARD Forward joystick switch JOY 0 1 DAT 9 xor 8 2 BACK Back joystick switch JOY 0 1 DAT 1 xor 0 3 LEFT Left joystick switch JOY 0...

Page 317: ...ence level while counter keeps track of the number of lines since the end of the reset interval 3 When the input voltage finally exceeds the internal threshold for a given input channel the current co...

Page 318: ...sweeps past the light pen a trigger pulse is generated which can be enabled to latch the horizontal and vertical beam positions There is no hardware bit to indicate this trigger but this can be deter...

Page 319: ...5V 270 ma maximum 410 ma surge When below 3 75V drives are required to reset their motor on flopa and set their write protect flops 13 SIDEB O Side 1 if active side 0 if inactive 14 WPRO I O Asserted...

Page 320: ...t is received first EXTERNAL DISK CONNECTOR DEFINED IDENTIFICATIONS 0000 0000 no drive present FFFF FFFF Amiga standard 3 25 diskette 5555 5555 48 TPI double density double sided As with other periphe...

Page 321: ...MTROD led 21 GND 5 GND 22 DKWDB 6 N C 23 GND 7 GND 24 DKWEB 8 IND B 25 GND 9 GND 26 TK0 10 SELOB 27 GND 11 GND 28 WPRO 12 N C 29 GND 13 GND 30 DKRD 14 N C 31 GND 15 GND 32 SIDEB 16 MTROD 33 GND 17 GN...

Page 322: ...P4 data 4 data PB3 P3 data 3 PB2 P2 data 2 PBl P1 data 1 PB0 P0 data 0 PC drdy Centronics control F ack Address BFDRFE data bits 15 8 A13 int6 PA7 com line DTR driven output PA6 com line RTS driven o...

Page 323: ...____________ PORT 1 __________________ POTOX o_ ________________________ o__ ___________ ____________ POTOY ______V_____________V______ POT1Y POT1X COUNTER COUNTER POT1DAT LATCH LATCH DFF014 _________...

Page 324: ...___ ___________________________________________________ FIRE FIRE PRA 1 0 BFE001 ______ ______ ______ ______ ______ ______ ______ ______ 7 0 ______________ ____________________________________________...

Page 325: ...________________________________ BPLCON0 write only DFF104 __ __ __ __ __ __ __ __ __ __ __ _ __ __ __ 15 3 0 ________Light Pen Enable ____________________________________________ POT1NP read only DFF...

Page 326: ...INTERFACE ADAPTOR CIA CHIPS Each Amiga system contains two 8520 Complex Interface Adaptor CIA chips Each chip has 16 general purpose input output pins plus a serial shift register three timers an out...

Page 327: ...AA control register A BFEF01 crb CIAA control register B Note CIAA can generate interrupt INT2 CIAB Address Map Byte Register Data bits Address Name 7 6 5 4 3 2 1 0 BFD000 pra DTR RTS CD CTS DSR SEL P...

Page 328: ...ial data register 1 1 0 1 D icr Interrupt control register 1 1 1 0 E cra Control register A I 1 1 1 F crb Control register B SOFTWARE NOTE The operating system kernel has already allocated the use of...

Page 329: ...using the PC output pin and the FLAG input pin PC will go low on the third cycle after a port B access This signal can be used to indicate data ready at port B or data accepted from port B Handshaking...

Page 330: ...he timer output to appear on a port B output line PB6 for timer A and PB7 for timer B This function overrides the DDRB control bit and forces the appropriate PB line to become an output TOGGLE PULSE A...

Page 331: ...load or following a write to the high byte of the pre scalar while the timer is stopped If the timer is running a write to the high byte will load the timer latch but not the counter BIT NAMES on READ...

Page 332: ...tart again until after a write to the LSB event register This assures that TOD will always start at the desired time Since a carry from one stage to the next can occur at any time with respect to a re...

Page 333: ...he speed at which the receiver responds to input data To begin transmission you must first set up Timer A in continuous mode and start the timer Transmission will start following a write to the serial...

Page 334: ...gister Any interrupt that is enabled by a 1 bit in that position in the MASK will set the IR bit MSB of the DATA register and bring the IRQ pin low In a multichip system the IR bit can be polled to de...

Page 335: ...ant to set the Timer A interrupt bit enable the Timer A interrupt but want to be sure that all other interrupts are cleared Here is the sequence you can use INCLUDE hardware cia i XREF ciaa From amiga...

Page 336: ...ccurs during one shot mode 1 PBON 1 Timer A output on PB6 0 PB6 is normal operation 2 OUTMODE 1 toggle 0 pulse 3 RUNMODE 1 one shot mode 0 continuous mode 4 LOAD 1 force load this is a strobe input th...

Page 337: ...rmal operation 2 OUTMODE 1 toggle 0 pulse RUNMODE 1 one shot mode 0 continuous mode 4 LOAD 1 force load this is a strobe input there is no data storage bit 4 will always read back a zero and writing a...

Page 338: ...programmer to relate the port addresses to the outside world items or internal control signals which are to be affected This part is primarily for the use of the systems programmer and should generall...

Page 339: ...PBl P1 data 1 PBO P0 data 0 PC drdy centronics control F ack Address BFDrOO data bit 15 8 A13 INT6 PA7 com line DTR driven output PA6 com line RTS driven output PA5 com line carrier detect PA4 com li...

Page 340: ...2148 INCLUDE hardware cia i INCLUDE hardware custom i XREF _ciaa XREF _ciab XREF _custom lea _custom a3 Base of custom chips lea _ciaa a4 Get base address if CIA A move w S7fff dmacon a3 Kill all chip...

Page 341: ...no other INTERFACE SIGNALS CLOCK INPUT The 02 clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system data bus On the Amiga this...

Page 342: ...NTERRUPT REQUEST OUTPUT IRQ is an open drain output normally connected to the processor interrupt input An external pull up resistor holds the signal high allowing multiple IRQ outputs to be connected...

Page 343: ...334 Appendix F...

Page 344: ...ard its address space preferences type of board memory or other and a unique Hardware Manufacturer Number assigned by Commodore Amiga Technical Support West Chester Pennsylvania Each board contains co...

Page 345: ...RAM boards without using the Amiga operating system Such applications should only configure expansion RAM boards boards which ask to be added to the free memory list and known dedicated boards designe...

Page 346: ...the first 80 bytes of an AUTOCONFIG board at configuration time NOTES o Identification information is stored in the high nibbles of the even word addresses at the start of an AUTOCONFIG board For exam...

Page 347: ...5 4 3 2 1 0___Board size 000 8meg 100512k Read __ __ 001 64k 101 1meg Not Inverted 010 128k 110 2meg 011 256k 111 4meg 1 Next card is also on this board 1 Optional ROM vector valid 1 Link into memory...

Page 348: ...erial 1st byte msb 1C lE 7 6 5 4 3 2 1 0 Optional serial 2nd byte 20 22 7 6 5 4 3 2 1 0 Optional serial 3rd byte 24 26 7 6 5 4 3 2 1 0 Optional serial 4th byte lsb Read Inverted S28 2A 7 6 5 4 3 2 1 0...

Page 349: ...re using the same interrupt line S44 46 7 6 5 4 3 2 1 0 Reserved read must be 00 R W Write undefined Inverted S48 4A 7 6 5 4 3 2 1 0 Base add register write only Write Only ___ ___ ___ ___ These bits...

Page 350: ...he board printf er Manufacturer printf d myCD cd Rom er Manufacturer printf S x myCD cd Rom er Manufacturer printf 4x n myCD cd Rom er Manufacturer printf er Product printf d myCD cd Rom er Product pr...

Page 351: ...342 Appendix G...

Page 352: ...y connections The four wires provide 5 volt power ground and signals called KCLK keyboard clock and KDAT keyboard data KCLK is unidirectional and always driven by the keyboard KDAT is driven by both t...

Page 353: ...compatibility with all keyboard models All codes transmitted to the computer are rotated one bit before transmission The transmitted order is therefore 6 5 4 3 2 1 0 7 The reason for this is to transm...

Page 354: ..._________ KDAT __________ ____ ____ 0 1 1 0 1 0 1 0 In the next example the B key is released The keycode is still 35 except that bit 7 is set to indicate key up resulting in a code of B5 10110101 Aft...

Page 355: ...to restore sync the garbage character thus transmitted will appear as a key release which is less dangerous than a key hit Whenever the keyboard detects that it has lost sync it will assume that the c...

Page 356: ...re synchronizing due to a handshake time out Once the keyboard and computer are in sync the keyboard must inform the computer of the results of the self test If the self test failed for any reason a...

Page 357: ...mal keystroke else the keyboard goes directly to Hard Reset On the second reset warning code the Amiga must drive KDAT low within 250 milliseconds else the keyboard goes directly to Hard Reset If the...

Page 358: ...no up down flag associated with them However the transmission bit order is the same as previously described CODE NAME MEANING 78 Reset warning CTRL AMIGA AMIGA has been hit computer will be reset in 1...

Page 359: ...Q PD 5 note 1 1 note 1 5E 31 20 10 01 5A 12 9 X S W f1 PD 4 note 3 2 3F 32 21 11 02 50 11 6 C D E f2 PD 3 note 3 3 2F 33 22 12 03 51 10 3 V F R f3 PD 2 note 3 4 1F 34 23 13 04 52 9 B G T f4 PD 1 note...

Page 360: ...1 A500 and A2000 keyboards only numeric pad note 2 International keyboards only these keys are cutouts of the larger key on the US ASCII version The key that generates 30 is cut out of the left shift...

Page 361: ...352 Appendix H...

Page 362: ...connector at the rear of the main computer unit is used to interface to and control devices that generate and receive MFM data This interface can be reached either as a resource or under the control...

Page 363: ...I O Track 0 16 DKWEB O Write gate 17 DKWDB O Write data 18 STEPB O Step 19 DIRB O Direction high is out 20 SEL3B O Select drive 3 21 SELlB O Select drive 1 22 INDEX I OO Index 23 12v PWR 120 mA averag...

Page 364: ...it has a write protected diskette installed INDEX Pin 22 A selected drive pulses this signal low once for each revolution of its motor SIDEB Pin 13 The system drives this signal to all disk drives low...

Page 365: ...oseconds after selecting the drive An external drives must have logic equivalent to a D flip flop whose D input is the MTRXD signal and whose clock input is activated by the off to on high to low tran...

Page 366: ...o a 16 bit word The most significant bit is the first value and so on This 16 bit quantity is the device I D The following I D s are defined 0000 0000 0000 0000 Reserved 1111 1111 1111 1111 Amiga stan...

Page 367: ...358 Appendix I...

Page 368: ...n Appendix A and Appendix B to names that can be resolved by the standard include files Use of these names in code sections of this manual places the emphasis on what the code is doing rather than get...

Page 369: ...o wait forever since the wait command described in it will never happen COPPER_HALT equ FFFFFFFE This is the offset in the 680x0 address space to the custom chip registers It is the same as custom whe...

Page 370: ...u bltcpt BLTCPTH equ bltcpt BLTCPTL equ bltcpt 02 BLTBPT equ bltbpt BLTBPTH equ bltbpt BLTBPTL equ bltbpt 02 BLTAPT equ bltapt BLTAPTH equ bltapt BLTAPTL equ bltapt 02 BLTDPT equ bltdpt BLTDPTH equ bl...

Page 371: ...C equ aud3 AUD3LCH equ aud3 AUD3LCL equ aud3 02 AUD3LEN equ aud3 04 AUD3PER equ aud3 06 AUD3VOL equ aud3 08 AUD3DAT equ aud3 0A The bitplane registers BPLlPT equ bplpt 00 BPLlPTH equ bplpt 00 BPLlPTL...

Page 372: ...rpt 1C SPR7PTH equ SPR7PT 00 SPR7PTL equ SPR7PT 02 Note SPRxDATB is defined as being 06 from SPRxPOS sd_datab should be defined as 06 however in the 1 3 assembler include file hardware custom i it is...

Page 373: ...COLOR03 equ color 06 COLOR04 equ color 08 COLOR05 equ color 0A COLOR06 equ color 0C COLOR07 equ color 0E COLOR08 equ color 10 COLOR09 equ color 12 COLOR10 equ color 14 COLOR11 equ color 16 COLOR12 eq...

Page 374: ...In sprites a mode in which a sprite uses two DMA channels for additional colors In sound production combining two audio channels for frequency amplitude modulation or for stereo sound AUTOMATIC MODE...

Page 375: ...g when sprites playfields or playfield objects attempt to overlap in the same pixel position or attempt to cross some pre defined boundary COLOR DESCRIPTOR WORDS Pairs of words that define each line o...

Page 376: ...es and video output DEPTH Number of bit planes in a display DIGITAL TO ANALOG CONVERTER A device that converts a binary quantity to an analog level DIRECT MEMORY ACCESS An arrangement whereby intellig...

Page 377: ...UTION A horizontal display mode in which 640 pixels are displayed across a horizontal line in a normal sized display HOLD AND MODIFY A display mode that gives you extended color selection up to 4 096...

Page 378: ...be aware of any other task NANOSECOND NS One billionth of a second 1 1 000 000 000 NON INTERLACED MODE A display mode in which 200 lines are displayed from top to bottom of the video display in a nor...

Page 379: ...al analog device used to adjust some variable value PRIMITIVES Amiga graphics text and animation library functions QUANTIZATION NOISE Audio noise introduced by round off errors when you are trying to...

Page 380: ...s to have full control over its own virtual 68000 machine TIMBRE Tone quality of a sound TRACKBALL A controller device that you spin with your hand to move something on the screen may have buttons for...

Reviews:

No comments

Brands by name

Popular brands

Load more brands