BIDIRECTIONAL FEATURE
The bi-directional capability of the shift register and CNT clock allows
many 8520s to be connected to a common serial communications bus on which
one 8520 acts as a master, sourcing data and shift clock while all other
8520 chips act as slaves. Both CNT and SP outputs are open drain to allow
such a common bus. Protocol for master/slave selection can be transmitted
over the serial bus or via dedicated handshake lines.
REG NAME D7 D6 D5 D4 D3 D2 D1 D0
--- ---- -- -- -- -- -- -- -- --
C SDR S7 S6 S5 S4 S3 S2 S1 S0
INTERRUPT CONTROL REGISTER (ICR)
There are five sources of interrupts on the 8520:
-Underflow from Timer A (timer counts down past 0)
-Underflow from Timer B
-TOD alarm
-Serial port full/empty
-Flag
A single register provides masking and interrupt information. The
interrupt control register consists of a write-only MASK register and a
read-only DATA register. Any interrupt will set the corresponding bit in
the DATA register. Any interrupt that is enabled by a 1-bit in that
position in the MASK will set the IR bit (MSB) of the DATA register and
bring the IRQ pin low. In a multichip system, the IR bit can be polled to
detect which chip has generated an interrupt request.
When you read the DATA register, its contents are cleared (set to 0), and
the IRQ line returns to a high state. Since it is cleared on a read, you
must assure that your interrupt polling or interrupt service code can
preserve and respond to all bits which may have been set in the DATA
register at the time it was read. With proper preservation and response,
it is easily possible to intermix polled and direct interrupt service
methods.
You can set or clear one or more bits of the MASK register without
affecting the current state of any of the other bits in the register.
This is done by setting the appropriate state of the MSBit, which is
called the set/clear bit. In bits 6-0, you yourself form a mask that
specifies which of the bits you wish to affect. Then, using bit 7, you
specify HOW the bits in corresponding positions in the mask are to be
affected.
- Appendix F 325 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...
