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SERPER 032 W P Serial port period and control
This register contains the control bit LONG referred to
above, and a 15-bit number defining the serial port
baud rate. If this number is N, then the baud rate is
1 bit every (N+1) * 0.2794 microseconds.
BIT# SYM FUNCTION
--------------------------------------------------------------
15 LONG Defines serial receive as 9-bit word.
14-00 RATE Defines baud rate=1/ ( (N+1) * 0.2794 microsec.
SPRxCTL 142 W A D Sprite x vert stop position and control data
SPRxPOS 140 W A D Sprite x vert-horiz start position data
These two registers work together as position, size and
feature sprite-control registers. They are usually loaded
by the sprite DMA channel during horizontal blank;
however, they may be loaded by either processor at any time.
SPRxPOS register:
BIT# SYM FUNCTION
------------------------------------------------------------------
15-08 SV7-SV0 Start vertical value. High bit(SV8) is in SPRxCTL
register below.
07-00 SH8-SH1 Start horizontal value. Low bit(SH0) is in SPRxCTL
register below.
SPRxCTL register (writing this address disables sprite horizontal
comparator circuit):
BIT# SYM FUNCTION
------------------------------------------------------------
15-08 EV7-EV0 End (stop) vertical value low 8 bits
07 ATT Sprite attach control bit (odd sprites)
06-04 X Not used
02 SV8 Start vertical value high bit
01 EV8 End (stop) vertical value high bit
00 SH0 Start horizontal value low bit
SPRxDATA 144 W D Sprite x image data register A
SPRxDATB 146 W D Sprite x image data register B
These registers buffer the sprite image data. They are
usually loaded by the sprite DMA channel but may be
loaded by either processor at any time. When a
horizontal comparison occurs, the buffers are dumped
into shift registers and serially outputted to the
display, MSB first on the left.
NOTE: Writing to the A buffer enables (arms) the sprite.
Writing to the SPRxCTL register disables the sprite.
If enabled, data in the A and B buffers will be outputted
whenever the beam counter equals the sprite horizontal
position value in the SPRxPOS register.
SPRxPOS see SPRxCTL
- 278 Appendix A -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...