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The following codes and abbreviations are used in this appendix:
& Register used by DMA channel only.
% Register used by DMA channel usually, processors sometimes.
+ Address register pair. Must be an even address pointing to chip
memory.
* Address not wriTable by the Copper.
- Address not wriTable by the Copper unless the "copper danger bit",
COPCON is set true.
A,D,P
A=Agnus chip, D=Denise chip, P=Paula chip.
W,R
W=write-only; R=read-only,
ER Early read. This is a DMA data transfer to RAM, from either the disk
or the blitter. RAM timing requires data to be on the bus earlier than
microprocessor read cycles. These transfers are therefore initiated
by Agnus timing, rather than a read address on the destination address
bus.
S Strobe (write address with no register bits). Writing the register
causes the effect.
PTL,PTH
Chip memory pointer that addresses DMA data. Must be reloaded by a
processor before use (vertical blank for bit-plane and sprite
pointers, and prior to starting the blitter for blitter pointers).
LCLLCH
Chip memory location (starting address) of DMA data. Used to
automatically restart pointers, such as the Copper program counter
(during vertical blank) and the audio sample counter (whenever the
audio length count is finished).
MOD
15-bit modulo. A number that is automatically added to the memory
address at the end of each line to generate the address for the
beginning of the next line. This allows the blitter (or the display
window) to operate on (or display) a window of data that is smaller
than the actual picture in memory (memory map). Uses 15 bits, plus
sign extend.
- 282 Appendix B -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...