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RSRS0 - ADDRESS INPUTS
The address inputs select the internal registers as described by the
register map.
DB7-DB0 - DATA BUS INPUTS/OUTPUTS
The eight data bus output pins transfer information between the 8520 and
the system data bus. These pins are high impedance inputs unless CS is
low and R/W and 02 are high, to read the device. During this read, the
data bus output buffers are enabled, driving the data from the selected
register onto the system data bus.
IRQ - INTERRUPT REQUEST OUTPUT
IRQ is an open drain output normally connected to the processor interrupt
input. An external pull-up resistor holds the signal high, allowing
multiple IRQ outputs to be connected together.
The IRQ output is normally off (high impedance) and is activated low as
indicated in the functional description.
RES - RESET INPUT
A low on the RES pin resets all internal registers. The port pins are set
as inputs and port registers to zero (although a read of the ports will
return all highs because of passive pull-ups). The timer control registers
are set to zero and the timer latches to all ones. All other registers
are reset to zero.
- Appendix F 333 –
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...