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All Copper instructions consist of two 16-bit words in sequential memory locations. Each
time the Copper fetches an instruction, it fetches both words. The MOVE and SKIP
instructions require two memory cycles and two instruction words. Because only the odd
memory cycles are requested by the Copper, four memory cycle times are required per
instruction. The WAIT instruction requires three memory cycles and six memory cycle
times; it takes one extra memory cycle to wake up.
Although the Copper can directly affect only machine registers, it can affect the memory
by setting up a blitter operation. More information about how to use the Copper in
controlling the blitter can be found in the sections called "Control Register" and "Using the
Copper with the Blitter."
The WAIT and MOVE instructions are described below. The SKIP instruction is described in
the "Advanced Topics" section.
THE MOVE INSTRUCTION
The MOVE instruction transfers data from RAM to a register destination. The transferred
data is contained in the second word of the MOVE instruction; the first word contains the
address of the destination register. This procedure is shown in detail in the section called
"Summary of Copper Instructions."
FIRST INSTRUCTION WORD (IR1)
Bit 0 Always set to 0.
Bits 8 - 1 Register destination address (DA8-1).
Bits 15 - 9 Not used, but should be set to 0.
SECOND INSTRUCTION WORD (IR2)
Bits 15 - 0 16 bits of data to be transferred (moved) to the register
destination.
- Coprocessor Hardware 15 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...