
Table 8-9 shows the definitions of the various bit positions within SERDATR.
Table 8-9: SERDATR / ADKCON Registers
SERDATR
Bit
Number Name Function
15 OVRUN OVERRUN bit
(Mirror - also appears in the interrupt request
register.) Indicates that another byte of data was
received before the previous byte was picked up by the
processor. To prevent this condition, it is necessary
to reset INTF_RBF (bit 11, receive-buffer-full) in
INTREQ.
14 RBF READ BUFFER FULL
(Mirror - also appears in the interrupt request
register.) When this bit is 1, there is data ready to
be picked up by the processor. After reading the
contents of this data register, you must reset the
INTF_RBF bit in INTREQ to prevent an overrun.
13 TBE TRANSMIT BUFFER EMPTY
(Not a mirror-interrupt occurs when the buffer becomes
empty.) When bit 14 is a 1, the data in the output data
register (SERDAT) has been transferred to the serial
output shift register, so SERDAT is ready to accept
another output word. This is also true when the buffer
is empty.
This bit is normally used for full-duplex operation.
12 TSRE TRANSMIT SHIFT REGISTER EMPTY
When this bit is a 1, the output shift register has
completed its task, all data has been transmitted, and
the register is now idle. If you stop writing data into
the output register (SERDAT), then this bit will become
a 1 after both the word currently in the shift register
and the word placed into SERDAT have been transmitted.
This bit is normally used for half-duplex operation.
11 RXD Direct read of RXD pin on Paula chip.
10 Not used at this time.
9 STP Stop bit if 9 data bits are specified for receive.
- 252 Interface Hardware -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...