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After turning on the motor, software must further wait
for one half second (500ms), or for the DSKRDY* line to
go low.
PB6 DSKSEL3* Select drive 3 (active low).
PB5 DSKSEL2* Select drive (active low).
PB4 DSKSEL1* Select drive 1 (active low).
PB3 DSKSEL0* Select drive 0 (internal drive) (active low).
PB2 DSKSIDE Specify which disk head to use. Zero indicates the
upper head. DSKSIDE must be sTable for 100
microseconds before writing. After writing, at least
1.3 milliseconds must pass before switching DSKSIDE.
PB1 DSKDIREC Specify the direction to seek the heads. Zero implies
seek towards the centre spindle. Track zero is at the
outside of the disk. This line must be set up before
the actual step pulse, with a separate write to the
register.
PB0 DSKSTEP* Step the heads of the disk. This signal must always be
used as a quick pulse (high, momentarily low, then high).
The drives used for the Amiga are guaranteed to get to
the next track within 3 milliseconds. Some drives will
support a much faster rate, others will fail. Loops
that decrement a counter to provide delay are not
accepTable. See Appendix F for a better solution.
When reversing directions, a minimum of 18 milliseconds
delay is required from the last step pulse. Settle time
for Amiga drives is specified at 15 milliseconds.
FLAG DSKINDEX* Disk index pulse ($BFDD00, bit 4). Can be used to
create a level 6 interrupt. See Appendix F for details.
- Interface Hardware 239 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...