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As mentioned above, the blitter normally has a higher priority than the processor for DMA
cycles. There are certain cases, however, when the blitter and the 68000 can share
memory cycles. If given the chance, the blitter would steal every available memory cycle.
Display, disk, and audio DMA take precedence over the blitter, so it cannot block them
from bus access. Depending on the setting of the blitter DMA mode bit, commonly
referred to as the "blitter-nasty" bit, the processor may be blocked from bus access. This
bit is called DMAF BLITHOG and is in register DMACON.
If DMAF_BLITHOG is a 1, the blitter will keep the bus for every available memory cycle.
This could potentially be every cycle.
If DMAF_BLITHOG is a 0, the DMA manager will monitor the 68000 cycle requests. If the
68000 is unsatisfied for three consecutive memory cycles, the blitter will release the bus
for one cycle.
BLITTER BLOCK DIAGRAM
Figure 6-13 shows the basic building blocks for a single bit of a 16-bit wide operation of
the blitter. It does not cover the line-drawing hardware.
o The upper left comer shows how the first - and last - word masks are applied to the
incoming A-source data. When the blit shrinks to one word wide, both masks are applied.
o The shifter (upper right and centre left) drawing illustrates how 16 bits of data is taken
from a specified position within a 32-bit register, based on the A shift or B shift values
shown in BLTCON0 and BLTCON1.
o The minterm generator (centre right) illustrates how the minterm select bits either allow
or inhibit the use of a specific minterm.
o The drawing shows how the fill operation works on the data generated by the minterm
combinations. Fill operations can be performed simultaneously with other complex logic
operations.
o At the bottom, the drawing shows that data generated for the destination can be
prevented from being written to a destination by using one of the blitter control bits.
o Not shown on this diagram is the logic for zero detection, which looks at every bit
generated for the destination. If there are any 1-bits generated, this logic indicates that
the area of the blit contained at least one 1-bit (zero detect is false.)
- Blitter Hardware 193 -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...