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The C and D pointer registers should be initialized to the word containing the first pixel of
the line; the C and D modulo registers should be set to the width of the bitplane in bytes.
The SRCA, SRCC, and DEST bits of BLTCON0 should be set to one, and the SRCB flag
should be set to zero. The OVFLAG should be cleared. If only a single bit per horizontal
row is desired, the ONEDOT bit of BLTCON1 should be set; otherwise it should be cleared.
The logic function remains. The C DMA channel represents the original source, the A
channel the bit to set in the line, and the B channel the pattern to draw. Thus, to draw a
line, the function AB+AC is the most common. To draw the line using exclusive-or mode,
so it can be easily erased by drawing it again, the function ABC+AC can be used.
We set the blit height to the length of the line, which is dx + 1. The width must be set to
two for all line drawing. (Of course, the BLTSIZE register should not be written until the
very end, when all other registers have been filled.)
REGISTER SUMMARY FOR LINE MODE
Preliminary setup:
The line goes from (x1 ,y1) to (x2,y2).
dx = max (abs (x2 - x1), abs (y2 - y1) )
dy = min (abs (x2 - x1), abs (y2 - y1) )
Register setup:
BLTADAT = $8000
BLTBDAT = line texture pattern ($FFFF for a solid line)
BLTAFWM = $FFFF
BLTALWM = $FFFF
BLTAMOD = 4 * (dy-dx)
BLTBMOD = 4 * dy
BLTCMOD = width of the bitplane in bytes
BLTDMOD = width of the bitplane in bytes
BLTAPT = (4 * dy) - (2 * dx)
BLTBPT = unused
BLTCPT = word containing the first pixel of the line
BLTDPT = word containing the first pixel of the line
- 186 Blitter Hardware -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...