
HARDWARE CONNECTION DETAILS
The system hardware selects the CIAs when the upper three address bits
are 101. Furthermore, CIAA is selected when A12 is low, A13 high; CIAB is
selected when A12 is high, A13 low. CIAA communicates on data bits 7-0,
CIAB communicates on data bits 15-8.
Address bits A11, A10, A9, and A8 are used to specify which of the 16
internal registers you want to access. This is indicated by "r" in the
address. All other bits are don't cares. So, CIAA is selected by the
following binary address: 101x xxxx xx01 rrrr xxxx xxx0. CIAB address:
101x xxxx xx10 rrrr xxxx xxx1
With future expansion in mind, we have decided on the following
addresses: CIAA = BFEr01; CIAB = BFDr00. Software must use byte accesses
to these address, and no other.
INTERFACE SIGNALS
CLOCK INPUT
The 02 clock is a TTL compatible input used for internal device operation
and as a timing reference for communicating with the system data bus. On
the Amiga, this is connected to the 68000 "E" clock. The "E" clock runs
at 1/10 of the CPU clock. This works out to .715909 Mhz for NTSC or
.709379 Mhz for PAL.
CS - CHIP-SELECT INPUT
The CS input controls the activity of the 8520. A low level on CS while
02 is high causes the device to respond to signals on the R/W and address
(RS) lines. A high on CS prevents these lines from controlling the 8520.
The CS line is normally activated (low) at 02 by the appropriate
address combination.
R/W - READ/WRITE INPUT
The RW signal is normally supplied by the microprocessor and controls the
direction of data transfers of the 8520. A high on R/W indicates a read
(data transfer out of the 8520), while a low indicates a write (data
transfer into the 8520).
- 332 Appendix F -
Summary of Contents for Amiga A1000
Page 1: ...AMIGA HARDWARE REFERENCE MANUAL 1992 Commodore Business Machines Amiga 1200 PAL...
Page 20: ...Figure 1 1 Block Diagram for the Amiga Computer Family Introduction 11...
Page 21: ...12 Introduction...
Page 72: ...Figure 3 12 A dual Playfield display Playfield Hardware 63...
Page 87: ...Figure 3 24 Horizontal Scrolling 78 playfield hardware...
Page 101: ...92 Playfield Hardware...
Page 199: ...Figure 6 9 DMA time slot allocation 190 Blitter hardware...
Page 203: ...Figure 6 13 Blitter Block Diagram 194 Blitter Hardware...
Page 229: ...220 System Control Hardware...
Page 246: ...Figure 8 8 Chinon Timing diagram cont Interface Hardware 237...
Page 265: ...256 Interface Hardware...
Page 289: ...280 Appendix A...
Page 297: ...288 Appendix B...
Page 298: ...APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE Means an active low signal Appendix C 289...
Page 302: ...APPENDIX D SYSTEM MEMORY MAP Appendix D 293...
Page 343: ...334 Appendix F...
Page 351: ...342 Appendix G...
Page 361: ...352 Appendix H...
Page 367: ...358 Appendix I...