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Altera Stratix II GX, User Manual

The Altera Stratix II GX User Manual is your essential guide to understanding and utilizing all the features of this powerful product. Easily accessible for download and free of charge at manualshive.com, this comprehensive manual empowers users to maximize the full potential of the Altera Stratix II GX.

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Altera Corporation 

  

2–117

October 2007

Stratix II GX Device Handbook, Volume 2

Stratix II GX Transceiver Architecture Overview

Two critical aspects related to PLD-controlled byte ordering process are:

■

What to choose as the byte ordering pattern 

■

When to assert the 

rx_enabyteord

 signal

In Stratix II GX configurations, PLD-controlled byte ordering is available 
only in SONET/SDH OC-48 mode or Basic double-width mode. In 
SONET/SDH OC-48 mode, byte A2 of the A1A2 word alignment pattern 
is automatically selected as the byte ordering pattern. In Basic 
Double-Width mode, you programs the byte ordering pattern while 
configuring the transceiver using the MegaWizard Plug-In Manager. 
Since the byte ordering block is designed to place the byte ordering 
pattern at the LSByte position, you must select a pattern that appears at 
the LSByte position at the source. This ensures that when the byte 
ordering block pushes the byte ordering pattern byte to the LSByte 
position at the receiver, the data is correctly byte ordered. Ideally, if this 
pattern is unique and is guaranteed to appear only at the LSByte position 
at the source, the instance at which the 

rx_enabyteord

 signal is 

asserted becomes irrelevant. For example, in packet-based 8B/10B 
encoded links, you could choose the Start of Packet (SOP) byte as the byte 
ordering pattern if it is a unique control code (say K28.0). In non 8B/10B 
scrambled data links, it may be difficult to find a unique pattern since 
there is a possibility of the pattern appearing in the scrambled payload 
and causing the byte ordering block to add pad bytes incorrectly. In such 
cases, the instance at which the 

rx_enabyteord

 signal is asserted 

becomes critical.

The 

rx_enabyteord

 signal must be asserted after the word aligner has 

aligned to the correct word boundary. This ensures that the byte ordering 
block does not find a byte ordering pattern between the word boundaries. 
If the 

rx_enabyteord

 signal is asserted before the intended byte 

ordering byte appears at the receiver, then the byte ordering block will 
add necessary pad bytes to achieve correct byte ordering. If the 

rx_enabyteord

 signal is asserted before the unintended data byte that 

matches the byte ordering pattern, then the byte ordering block may 
incorrectly add pad bytes and assert the 

rx_byteorderalignstatus

 

signal. In the SONET/SDH OC-48 configuration, since the receiver 
anticipates the byte ordering pattern A2 every 125

μ

s, the 

rx_enabyteord

 signal assertion can be easily timed to avoid incorrect 

byte ordering. In Basic Double-Width mode, it is up to you to either select 
a unique byte ordering pattern or an appropriate instance to assert 

rx_enabyteord

, depending on the dynamics of the implemented 

protocol.

Summary of Contents for Stratix II GX

Page 1: ...ters Chapter 1 Stratix II GX Transceiver Block Overview Chapter 2 Stratix II GX Transceiver Architecture Overview Chapter 3 Stratix II GX Dynamic Reconfiguration Chapter 4 Stratix II GX ALT2GXB Megafunction User Guide Chapter 5 Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide Chapter 6 Specifications Additional Information Revision History Refer to each chapter for its own specific revision ...

Page 2: ...Section I 2 Altera Corporation Preliminary Stratix II GX Transceiver User Guide Stratix II GX Device Handbook Volume 2 ...

Page 3: ... path through the transceiver and supports data rates from 600 Mbps to 3 125 Gbps Double width mode has a 16 bit 20 bit SERDES data path through the transceiver and supports data rates from 1 Gbps to 6 375 Gbps All blocks in the transceiver can operate in double width mode except deskew first in first out FIFO which is available only in single width mode The options for blocks available in the tra...

Page 4: ...ief description about the various components within the transmitter block Figure 1 2 The modules are listed in order from the parallel logic array to the transmit buffer of the transmitter Figure 1 2 Stratix II GX Transmitter Block Diagram Receiver Analog Circuits Receiver Digital Logic De serializer Clock Recovery Unit Receiver PLL Deskew FIFO Word Aligner Rate Match FIFO 8B 10B Decoder Byte De s...

Page 5: ... modes and cannot be bypassed Byte Serializer The byte serializer allows the programmable logic device PLD to run at half the rate of the transmit data path to allow the core to run at a lower frequency Without the byte serializer at the maximum data rate of 6 375 Gbps with a 20 bit serialization factor the PLD transceiver interface needs to run at 318 75 MHz The PLD transceiver interface can run ...

Page 6: ...elps compensate for high frequency losses A variety of programmable voltage output differential VOD settings allow noise margin tuning capabilities Additionally on chip termination OCT provides the appropriate transmitter buffer termination for 100 120 or 150 Ω transmission lines The transmitter buffer circuit also contains a receiver detect circuit for use with the PCI Express PIPE protocol to de...

Page 7: ... in the transceiver has a dedicated receiver PLL that provides clocking flexibility and supports a range of data rates These PLLs generate the required clock frequencies based upon the synthesis of an input reference clock Clock Recovery Unit The Stratix II GX transceiver block CRU performs analog clock data recovery CDR The CRU recovers the embedded clock in the data stream to properly clock the ...

Page 8: ... bit patterns Channel Aligner Deskew An embedded channel aligner aligns byte boundaries across multiple channels and synchronizes the data entering the logic array from the Gigabit transceiver block s four channels The Stratix II GX channel aligner is optimized for a 10 Gigabit Ethernet XAUI four channel implementation The channel aligner includes the control circuitry and channel alignment charac...

Page 9: ...e PLD interface to reduce the rate at which the received data must be clocked in the PLD logic This byte deserializer block is available in both single and double width modes In single width mode the PLD interface is either 16 or 20 bits when used In double width mode using the byte deserializer creates a PLD interface of 32 or 40 bits depending on your serialization factor Byte Ordering Each rece...

Page 10: ... Test The gigabit transceiver block contains several features that simplify design verification Embedded pattern generators and pattern verifiers provide a simple approach to board verification without the need to design additional logic in the PLD fabric The BIST pseudo random binary sequence PRBS and incremental pattern generators along with their respective pattern verifiers provide a full self...

Page 11: ...er in volume 2 of the Stratix II GX Device Handbook Document Revision History Table 1 1 shows the revision history for this chapter Table 1 1 Document Revision History Part 1 of 2 Date and Document Version Changes Made Summary of Changes October 2007 v2 4 Added note to Receiver Differential Input Buffers section Updated bulleted list in Building Blocks and Loopback sections Updated Clock Multiplie...

Page 12: ...d 1 3 February2006 v2 0 Updated Building Blocks section Updated Word Aligner section Updated Byte Ordering section Updated Loopback section Updated Built In Self Test section October 2005 v1 0 Added chapter to the Stratix II GX Device Handbook Table 1 1 Document Revision History Part 2 of 2 Date and Document Version Changes Made Summary of Changes ...

Page 13: ...ut rx_datain rx_enapatternalign rx_a1a2size rx_bitslip pll_inclk pipe8b10binvpolarity rx_digitalreset rx_analogreset rx_locktodata rx_seriallpbken rx_locktorefclk gxb_powerdown rx_cruclk tx_datain gxb_enable reconfig_togxb tx_ctrlenable tx_detectrxloopback tx_forceelecidle tx_forcedispcompliance powerdn cal_blk_powerdown cal_blk_clk tx_digitalreset fixedclk rx_dataout pipephydonestatus rx_patternd...

Page 14: ...hase compensation FIFO If selected you must drive this port with a clock that is frequency locked to rx_clkout tx_clkout Channel rx_enapatternalign Input Enables word aligner to align to the comma This port can either be edge or level sensitive based on the word aligner mode In the double width mode this port is only edge sensitive Channel rx_bitslip Input Word aligner bit slip control The word al...

Page 15: ...width is two parallel clock cycles Channel rx_bisterr Output Built in self test BIST block error flag This port latches high if an error is detected Assertion of rx_digitalreset resets the BIST verifier which clears the error flag Channel rx_bistdone Output Built in self test verifier done flag This port goes high if the receiver finishes reception of the test sequence Channel rx_ctrldetect Output...

Page 16: ...gnment options 0 16 bit A1A2 1 32 bit A1A1A2A2 Channel rx_a1a2sizeout Output Available only in SONET SDH OC 12 and OC 48 modes to indicate one of the following two word alignment options 0 16 bit A1A2 1 32 bit A1A1A2A2 Channel rx_invpolarity Input Available in all modes except OIF CEI PHY Inverts the polarity of the received data at the input of the word aligner Channel rx_revbitorderwa Input Avai...

Page 17: ...ct is forced high and must not be used as an indication of a valid signal at receiver input Channel rx_seriallpbken Input Serial loopback control port 0 normal data path no serial loopback 1 serial loopback Channel rx_locktodata Input Lock to data control for the CRU Use with rx_locktorefclk Channel rx_locktorefclk Input Lock to reference lock mode for the CRU Use with rx_locktodata rx_locktodata ...

Page 18: ...s port sets the power mode of the associated PCI Express channel The power modes are as follows 2 b00 P0 Normal operation 2 b01 P0s Low recover time latency power saving state 2 b10 P1 Longer recovery time 64 us max latency lower power state 2 b11 P2 Lowest power state Channel tx_digitalreset Input Reset port for the transmitter PCS block This port resets all the digital logic in the transmit chan...

Page 19: ...ut from the central clock generation block In 8 mode the central clock generator block from the lower transceiver generates this clock For use with XAUI PCI Express 4 and 8 modes Transceiver block reconfig_clk Input Input reference clock for the dynamic reconfiguration controller The frequency range of this clock is 2 5 MHz to 50 MHz The assigned clock uses global resources by default This same cl...

Page 20: ...Transmitter serial output port Channel rx_datain Input Receiver serial input port Channel rrefb 1 Output Reference resistor port This port is always used and must be tied to a 2K Ωresistor to ground This port is highly sensitive to noise There must be no noise coupled to this port Device refclk 1 Input Dedicated reference clock inputs two per transceiver block for the transceiver The buffer struct...

Page 21: ...r the PLD or the dedicated reference clock inputs refclk0 and refclk1 and synthesizes the clocks that are used for the transmitter logic serializer receiver PLL reference clock and PLD clocks Each transceiver block has its own CMU block that is further divided into three CMU sub blocks Transmitter PLL block Central clock divider block Transmitter local clock divider block The transmitter PLL block...

Page 22: ...Reference Clock Pin Specifications Table 2 3 shows the I O standards allowed for the reference clock pins Transmitter PLL Block Central Clock Divider Block TX Clock Gen Block TX Clock Gen Block Transmitter Channel 3 2 Transmitter Channel 1 0 Transmitter High Speed Low Speed Clocks Transmitter High Speed Low Speed Clocks Transmitter Local Clock Divider Block Transmitter Local Clock Divider Block Re...

Page 23: ... block multiplies the reference clock to the frequency required to support the serial data rate Transmitter PLL0 and transmitter PLL1 can support data rates from 600 Mbps to 6 375 Gbps Each PLL has a dedicated locked signal pll_locked that is fed to the PLD logic array to indicate when the PLLs are locked to the reference clock PIPE 1 2 V PCML 1 5 V PCML 3 3 V PCML Differential LVPECL LVDS AC On c...

Page 24: ...o reference clocks for the transmitter PLLs in a single transceiver block at any given time The reference clocks can come from the following Dedicated reference clock pins of the associated transceiver blocks two total per transceiver block PLD clock network one per transceiver block must be connected directly from an input clock pin and cannot be driven by user logic or enhanced PLL Inter transce...

Page 25: ...either transmitter PLL0 or transmitter PLL1 You can divide the reference clocks from the REFCLK pins by two to support higher reference clock frequencies Transmitter PLL0 and transmitter PLL1 have half rate VCOs that operate at half the rate of the serial data stream The range of these VCOs are from 500 MHz to 3 1875 GHz to support a native data rate of 1 Gbps to 6 375 GHz Lower data rates 600 Mbp...

Page 26: ... 2 2 This block provides the high speed clock for the serializer and the low speed clock for the transceiver s PCS logic within the transceiver block in a four lane mode In Physical Interface for PCI Express PIPE 8 mode the central clock divider block also provides the high speed clock and low speed clock for the adjacent upper transceiver block and provides the high and low speed clocks to the as...

Page 27: ...Clock Connection The central clock divider block feeds all the channels in the transceiver block and in PIPE 8 mode it also feeds the adjacent upper transceiver block This ensures that the serializer in each channel outputs the same bit number at the same time and minimizes the channel to channel skew 4 5 8 or 10 High Speed Transmitter PLL Clock Slow Speed Clock From Lower Transceiver Block High S...

Page 28: ...lock divider block is operated independently so there is no guarantee that each channel sends out the same bit at the same time Clock Synthesis Each PLL in a transceiver block receives a reference clock and generates a high speed clock that is forwarded to the clock generator blocks There are two types of clock generators the transmitter local clock divider block the central clock divider block Th...

Page 29: ...factor In the four lane mode the central clock divider block supplies all the necessary clocks for the entire transceiver block The reference clock ranges from 50 MHz to 622 08 MHz The phase frequency detector PFD has a minimum frequency limit of 50 MHz and a maximum frequency limit of 325 MHz The refclk pre divider 2 is available if you use the dedicated refclk pins for the input reference clock ...

Page 30: ...ing filters out internal noise from the VCO because it tracks the input clock above the frequency of the internal VCO noise With the low bandwidth setting if the noise on the input reference clock Table 2 5 Multiplication Values as a Function of the Reference Clock Source to the Transmitter PLL Transmitter PLL Reference Clock Source Reference Clock Pre Divider M 2 L Inter transceiver routing 1 2 1...

Page 31: ...inter transceiver lines offer flexibility when multiple channels in separate transceiver blocks share a common reference clock frequency The inter transceiver lines only distribute the reference clock and cannot be used to bond channels because each PLL and clock dividers operate independently If you select an input reference clock frequency such that it requires the use of the REFCLK pre divider ...

Page 32: ...IPE mode uses the eight lane configuration Single Lane In a single lane configuration the PLLs in the central block supply the high speed clock and the clock generation blocks in each transmitter channel divides down that clock to the frequency needed to support its particular data rate In this configuration two separate clocks can be supplied through the central block to provide support for two s...

Page 33: ...omatically chooses the single lane configuration Figure 2 9 Clock Distribution for Individual Channel Configuration Four Lane Mode In a four lane configuration Figure 2 10 the central block generates the parallel and serial clocks that feed the transmitter channels within the transceiver All channels in a transceiver must operate at the same data rate This configuration is only supported in PIPE 4...

Page 34: ...g that offers low skew for transmitter channel to channel skew specification The high and low speed clocks are forwarded using this dedicated eight lane clocking tree The central block of the upper transceiver block and all the transmitter clock generation blocks are unused and are powered down in this mode The clock to the PLD coreclkout is generated by the central clock generation block of the m...

Page 35: ...coupled to the lower master transceiver block The Quartus II software automatically utilizes the correct transceiver blocks in a 8 mode if you do not assign placement If you do not place the master and slave transceiver blocks accordingly through pin assignments a no fit error occurs Transmitter Channel 0 Transmitter Channel 1 Transmitter Channel 2 Central Block Transmitter Channel 0 Transmitter C...

Page 36: ... shows how double transceiver block devices EP2SGX30D and EP2SGX60D are configured for PCI E 8 mode Figure 2 12 Two Transceiver Block Device With One 8 PCI E Link GXB_TX RX1 GXB_TX RX0 GXB_TX RX2 GXB_TX RX3 GXB_TX RX5 GXB_TX RX4 GXB_TX RX6 GXB_TX RX7 EP2SGX30DF EP2SGX60DF PCIe Lane 4 PCIe Lane 5 PCIe Lane 7 PCIe Lane 6 PCIe Lane 0 PCIe Lane 1 PCIe Lane 3 PCIe Lane 2 Bank 13 Slave Bank 14 Master ...

Page 37: ...ion Figure 2 13 Three Transceiver Block Device With One 8 PCI E Link Note 1 Note to Figure 2 13 1 Transceiver Bank 15 can be active and used to support other protocols GXB_TX RX1 GXB_TX RX0 GXB_TX RX2 GXB_TX RX3 GXB_TX RX5 GXB_TX RX4 GXB_TX RX6 GXB_TX RX7 EP2SGX60EF EP2SGX90EF PCIe Lane 4 PCIe Lane 5 PCIe Lane 7 PCIe Lane 6 PCIe Lane 0 PCIe Lane 1 PCIe Lane 3 PCIe Lane 2 Bank 13 Slave Bank 14 Mast...

Page 38: ... protocols Figure 2 14 Four Transceiver Block Device With Two 8 PCI E Links GXB_TX RX1 GXB_TX RX0 GXB_TX RX2 GXB_TX RX3 GXB_TX RX5 GXB_TX RX4 GXB_TX RX6 GXB_TX RX7 EP2SGX90FF PCIe Lane 4 PCIe Lane 5 PCIe Lane 7 PCIe Lane 6 PCIe Lane 0 PCIe Lane 1 PCIe Lane 3 PCIe Lane 2 Bank 13 Slave Bank 14 Master GXB_TX RX9 GXB_TX RX8 GXB_TX RX10 GXB_TX RX11 GXB_TX RX13 GXB_TX RX12 GXB_TX RX14 GXB_TX RX15 PCIe L...

Page 39: ...nsceiver Block Device With Two 8 PCI E Links Note 1 Note to Figure 2 15 1 Transceiver Bank 17 can be active and used to support other protocols GXB_TX RX1 GXB_TX RX0 GXB_TX RX2 GXB_TX RX3 GXB_TX RX5 GXB_TX RX4 GXB_TX RX6 GXB_TX RX7 EP2SGX130GF PCIe Lane 4 PCIe Lane 5 PCIe Lane 7 PCIe Lane 6 PCIe Lane 0 PCIe Lane 1 PCIe Lane 3 PCIe Lane 2 Bank 13 Slave Bank 14 Master GXB_TX RX9 GXB_TX RX8 GXB_TX RX...

Page 40: ...ter channel from the PLD logic Figure 2 16 shows the clock routing for the transmitter channel Figure 2 16 Individual Channel Transmitter Logic Clocking The receiver logic clocking has two clocking methods one when rate matching is used and the other when rate matching is not used If rate matching is used PIPE GIGE and Basic modes the receiver logic from the serializer to the rate matcher is clock...

Page 41: ... of the transceiver block clocks all 4 channels In PIPE 8 bonded channel mode the central clock divider of the master transceiver block clocks all 8 channels The transmitter logic up to the read port of the transmitter phase compensation FIFO buffer is clocked by the slow speed clock from the central block The PIPE interface and the write port of the transmitter phase compensation FIFO buffer is c...

Page 42: ...rough the PLD from the central block feeds the read side of the phase compensation FIFO buffer Figure 2 20 Receiver Channel Clocking in XAUI Mode In the PIPE 4 and PIPE 8 modes Figure 2 21 the local recovered clock feeds the logic up to the write port of the rate matcher FIFO buffer The slow clock from the central block feeds the rest of the logic up to the write port of the phase compensation FIF...

Page 43: ...ftware chooses low latency mode automatically for every mode except the PCI Express PIPE mode which automatically uses high latency mode In high latency mode the FIFO buffer is eight words deep Figure 2 22 Transmitter Phase Compensation FIFO Buffer The phase compensation FIFO buffer s read port is clocked by the transmitter PLL clock The write clock is fed by tx_clkout of the associated channel in...

Page 44: ...r is asserted high when the phase compensation FIFO gets either full or empty This feature is useful to verify the phase compensation FIFO overrun underflow condition as a probable cause of link errors Byte Serializer The byte serializer Figure 2 23 converts the two or four byte interface into a one or two byte wide data path for the transceiver from the PLD interface The PLD interface has a limit...

Page 45: ...ain signal is the input from the FPGA s logic array that has already passed through the transmitter phase compensation FIFO buffer Figure 2 24 Transmitter Byte Serializer In Figure 2 24 the LSB is transmitted before the MSB in the transmitter byte serializer For the input of D1 the output is D1LSB and then D1MSB 8B 10B Encoder The 8B 10B encoder refer to Figure 2 25 is part of the Stratix II GX tr...

Page 46: ... Encoder Note to Figure 2 25 1 The control signal is tx_ctrlenable Single Width Mode The 8B 10B encoder data path active in single width mode is highlighted in Figure 2 26 Figure 2 26 8B 10B Encoder Single Width Mode Note to Figure 2 26 1 The control signal is tx_ctrlenable 8B 10B Encoder MSByte dataout 19 10 From Byte Serializer datain 15 8 Control Signals 1 1 8B 10B Encoder LSByte dataout 9 0 da...

Page 47: ...on The tx_digitalreset signal resets the 8B 10B encoder During reset the running disparity registers and the data registers are cleared The 8B 10B encoder outputs a K28 5 pattern from the RD column continuously until tx_digitalreset goes low The input data and tx_ctrlenable signals are ignored during the reset state Once out of reset the 8B 10B encoder starts with a negative disparity RD and trans...

Page 48: ...ut When tx_ctrlenable is low the byte at tx_datain port of the transceiver is encoded as data Dx y When tx_ctrlenable is high the data at the tx_datain port is encoded as a Kx y code group The waveform in Figure 2 29 shows that the 2nd 0xBC is encoded as a control word K28 5 The rest of the tx_datain bytes are encoded as data Dx y Figure 2 29 Control Word Identification Waveform 1 The 8B 10B encod...

Page 49: ...mitted prior to the most significant byte Figure 2 30 shows the active 8B 10B encoder blocks in double width mode Figure 2 30 Active 8B 10B Encoder Blocks in Double Width Mode Note to Figure 2 30 1 The control signal is tx_ctrlenable 20 Bit Encoding In double width mode the cascaded 8B 10B encoders generate two 10 bit code groups from two 8 bit data and their respective control identifiers The 8B ...

Page 50: ...on the LSByte and three on the MSByte encoder for synchronizing before it starts encoding and transmitting the data on tx_datain If the reset signal for the 8B 10B encoder is asserted the 8B 10B decoder receiving the data may receive an invalid code error synchronization error control detect and or disparity error while tx_digitalreset is high Figure 2 32 shows the reset behavior of the 8B 10B enc...

Page 51: ...control code as identified by a high on the lower tx_ctrlenable bit s second clock cycle Figure 2 33 Control Word Identification Waveform The 8B 10B encoder does not check to see if the code word entered is one of the 12 valid codes If an invalid control code is entered the resultant 10 bit code may be encoded as an invalid code does not map to a valid Dx y or Kx y code or unintended valid Dx y co...

Page 52: ...maintain the current running disparity calculations if the forced disparity value on the tx_dispval bit happens to match the current running disparity or flip the current running disparity calculations if it does not If the forced disparity flips the current running disparity the down stream 8B 10B decoder may detect a disparity error which should be tolerated by the down stream device Figure 2 34...

Page 53: ...nning disparity at the end of time n 2 indicates that the K28 5 at the low byte position in time n 4 should be encoded with a positive disparity Since the tx_forcedisp is high at time n 4 the signal level of tx_dispval is used to convert the lower byte K28 5 to be encoded as a negative disparity code word As the upper bit of tx_forcedisp is low at n 4 the high byte K28 5 will take the current runn...

Page 54: ...x_invpolarity port inverts the polarity of every bit of the 8 bit or 10 bit input data word to the serializer in the transmitter data path In double width modes a high value on the tx_invpolarity port inverts the polarity of every bit of the 16 bit or 20 bit input data word to the serializer in the transmitter data path Since inverting the polarity of each bit has the same effect as swapping the p...

Page 55: ...erview Figure 2 36 illustrates the transmitter polarity inversion feature in a single width 10 bit wide data path configuration Figure 2 36 Transmitter Polarity Inversion in Single Width Mode 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 Output from transmitter PCS Input to transmitter PMA To Serializer tx _invpolarity HIGH ...

Page 56: ...e transmitter polarity inversion feature in double width 20 bit wide data path configuration Figure 2 37 Transmitter Polarity Inversion in Double Width Mode 1 0 1 0 0 0 0 0 1 1 Output from transmitter PCS Input to transmitter PMA To Serializer tx _invpolarity HIGH 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 ...

Page 57: ...rsal feature is enabled in Basic single width mode the 8 bit D 7 0 or 10 bit D 9 0 data at the input of the serializer gets rewired to D 0 7 or D 0 9 respectively If the Transmitter Bit Reversal feature is enabled in Basic double width mode the 16 bit D 15 0 or 20 bit D 19 0 data at the input of the serializer gets rewired to D 0 15 or D 0 19 respectively Flipping the parallel data using this feat...

Page 58: ...zer block supports 8 bit Figure 2 40 10 bit 16 bit and 20 bit words The 8 bit and 10 bit operations are for use in the single width mode and support the data rate range from 600 Mbps to 3 125 Gbps The 16 bit and 20 bit operations are for the double width mode and support the data rate range from 1 Gbps to 6 375 Gbps Output from transmitter PCS Input to transmitter PMA To Serializer TX Bit Reversal...

Page 59: ... block natively transmits the LSB of the word first Figure 2 40 Serializer Block In 8 bit Mode Figure 2 41 shows the serial bit order of the serializer block output In this example a constant 8 h6A 01101010 value is serialized and the serial data is transmitted from LSB to MSB Figure 2 41 Serializer Bit Order D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 8 Low Speed Parallel Clock High Speed Ser...

Page 60: ...fer The Stratix II GX transmitter buffers support 1 2 V and 1 5 V pseudo current mode logic PCML up to 6 375 Gbps and can drive 40 inches of FR4 trace across two connectors The transmitter buffer refer to Figure 2 42 has additional circuitry to improve signal integrity programmable output voltage programmable three tap pre emphasis circuit and internal termination circuitry and the capability to d...

Page 61: ...mitter buffer power VCCH of 1 2 V or 1 5 V through the ALT2GXB MegaWizard Plug In Manager the What is the transmit buffer power VCCH option The transmitter buffer power supply in Stratix II GX devices is transceiver based The 1 2 V power supply supports the 1 2 V PCML standard Single Ended Waveform Differential Waveform VA VB VOD VOD VOD VOD 0 V Differential 700 700 VOD Differential VA VB Table 2 ...

Page 62: ...rom the transmission medium The pre emphasis requirements increase as data rates through legacy backplanes increase The Stratix II GX transmitter buffer employs a pre emphasis circuit with up to 477 of pre emphasis to correct for losses in the transmission medium You set pre emphasis settings through a slider menu in the ALT2GXB MegaWizard Plug In Manager Specify the pre emphasis settings pre emph...

Page 63: ... the ALT2GXB MegaWizard Programmable Common Mode You can set the common mode in Stratix II GX devices to 600 mV or 700 mV Use the 600 mV setting with the 1 2 V PCML standard Use the 700 mV setting for the 1 5 V PCML standard Table 2 9 shows the available common mode settings for 1 2 V 1 5 V VCCH PCI Express Receiver Detect The Stratix II GX transmitter buffer has a built in receiver detection circ...

Page 64: ... puts the transmitter buffer in Electrical Idle mode This port is available in all PCI Express power down modes and has a specific use in each mode Table 2 10 shows the usage in each power mode Receiver Modules This section describes the Stratix II GX transceiver s receiver path This section describes the following modules Receiver buffer Receiver PLL Clock recovery unit Deserializer Word aligner ...

Page 65: ...Figure 2 44 Receiver Buffer Programmable Receiver Termination The Stratix II GX receiver buffer has an optional programmable on chip differential termination of 100 Ω 120 Ω or 150 Ω You can set the receiver termination resistance setting using one of the two ways Set the receiver termination resistance option in the MegaWizard if on chip termination is used The settings allowed are 100 Ω 120 Ω and...

Page 66: ...Data Modes on page 2 64 for more information regarding this process You can bypass the signal detect loss threshold detection circuit by choosing the Forced Signal Detect option in the MegaWizard This is useful in lossy environments where the voltage thresholds might not meet the lowest voltage threshold setting Forcing this signal high enables the receiver PLL to switch from VCO training based on...

Page 67: ...components are attenuated This equalizes the frequency response such that the delta between the low frequency and high frequency components are reduced which in return minimizes the ISI effects from the transmission medium 1 Stratix II GX receiver also offers the Adaptive Equalization AEQ feature If you enable this feature the equalizer circuit automatically selects and adjusts appropriate equaliz...

Page 68: ...transmitter common mode voltage and the receiver common mode voltage The external or on chip receiver termination and bias circuitry must ensure compatibility between the transmitter and the receiver common mode voltage Figure 2 46 shows a DC coupled link Figure 2 46 DC Coupled Link Trace Trace Transmitter Receiver DC Block DC Block TX VCM RX VCM 50 60 75 TX Termination Ω 50 60 75 RX Termination Ω...

Page 69: ... or both Specifically the following link configurations are discussed Stratix II GX Transmitter PCML to Stratix II GX Receiver PCML Stratix II GX Transmitter PCML to Stratix GX Receiver PCML Stratix GX Transmitter PCML to Stratix II GX Receiver PCML LVDS Transmitter to Stratix II GX Receiver PCML Stratix II GX Transmitter PCML to Stratix II GX Receiver PCML Figure 2 47 shows a typical Stratix II G...

Page 70: ...tings for a Stratix II GX to Stratix II GX DC Coupled Link Transmitter Stratix II GX Settings Receiver Stratix II GX Settings Data Rate VCCH 1 TX VCM 1 Differential Termination Data Rate RX VCM Differential Termination 600 6375 Mbps 1 2 V 1 5 V 0 6 V 0 7 V 100 120 150 Ω 600 6375 Mbps 0 85 V 100 120 150 Ω Note to Table 2 10 1 VCCH 1 2 V with TX Vcm 0 6 V can support data rates from 600 Mbps to 3125...

Page 71: ...Stratix GX DC Coupled Link Transmitter Stratix II GX Settings Receiver Stratix GX Settings Data Rate VCCH 1 TX VCM 1 Differential Termination Data Rate RX VCM Differential Termination 600 3187 5 Mbps 1 5 V 1 5 V PCML 0 6 V 0 7 V 100 120 150 Ω 600 3187 5 Mbps 1 1 V 100 120 150 Ω Note to Table 2 12 1 VCCH 1 5 V with TX Vcm 0 7 V can support data rates from 600 Mbps to 3125 Mbps VCCH 1 5 V with TX Vc...

Page 72: ...I GX DC Coupled Link Transmitter Stratix GX Settings Receiver Stratix II GX Settings Data Rate VCCH TX VCM Differential Termination Data Rate I O Standard RX VCM Differential Termination 600 3187 5 Mbps 1 5 V 0 75 V 100 120 150 Ω 600 3187 5 Mbps 1 5 V PCML 0 85 V 100 120 150 Ω Trace Trace Stratix II GX Receiver RX VCM 50 60 75 RX Termination Ω LVDS Transmitter 50 60 75 RX Termination Ω 1 2 V Rs Ta...

Page 73: ...in the section Clock Recovery Unit on page 2 63 For information on the operation between the lock to reference and lock to data modes refer to Lock to Reference and Lock to Data Modes on page 2 64 The receiver PLL has an optional lock indicator rx_pll_locked which indicates when the receiver PLL is phase and frequency locked to the reference clock The rx_pll_locked is an active high signal A high ...

Page 74: ...here the 622 MHz reference clock can be divided by 2 yielding a 311 MHz clock at the PFD The VCO runs at half the data rate so the selected multiplication factor should yield a 1244 MHz high speed clock The Quartus II software automatically selects a multiplication factor of 4 in this case to generate a 1244 MHz clock from the pre divided 311 MHz clock If the 2 pre divider is used the reference cl...

Page 75: ...nd jitter The bandwidth is determined by the 3dB frequency of the closed loop gain of the PLL A higher bandwidth setting helps reject noise from the VCO and power supplies A low bandwidth setting filters out more high frequency data input jitter Valid receiver bandwidth settings are low medium or high The 3dB frequencies for these settings vary because of the non linear nature and data dependencie...

Page 76: ... indicates the current mode of CRU lock to data or lock to reference After switching into lock to data mode assertion of the rx_freqlocked signal the CRU unit needs time to acquire phase lock to the incoming data stream For automatic transition from the lock to reference mode to the lock to data mode the following conditions must be met The serial data at the receiver input buffer is within the pr...

Page 77: ...k to data or lock to reference mode In lock to data mode the rx_freqlocked signal is high In lock to reference mode the rx_freqlocked signal is low In lock to data mode the rx_freqlocked signal is asserted and the rx_pll_locked signal loses its significance because the rx_pll_locked signal indicates that the CRU has locked to the reference clock When the CRU is in lock to data mode the phase of th...

Page 78: ...uce the time it takes for the CRU to switch from lock to reference mode to lock to data mode You can assert the rx_locktorefclk to initially train the CRU The rx_locktodata signal should be asserted after training the CRU When the rx_locktorefclk signal is asserted the rx_freqlocked signal does not have any significance because it is low indicating that the CRU is in lock to reference mode If lock...

Page 79: ...lel data rate is 2 5 10 or 250 MHz The first bit into the deserializer block is the LSB of the data bus out Figure 2 53 Deserializer Block in 8 Bit Mode Figure 2 54 shows the serial bit order of the deserializer block input and the parallel data out of the deserializer block Figure 2 54 shows a serial stream 01101010 deserialized into a value 8 h6A 01101010 The serial data is received LSB to MSB 1...

Page 80: ...olarity of every bit of the 16 bit or 20 bit input data word to the word aligner in the receiver data path Since inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link correct data is seen by the receiver The rx_invpolarity is a dynamic signal and may cause initial disparity errors in an 8B 10B encoded link The downstream syste...

Page 81: ...ure Overview Figure 2 55 illustrates the receiver polarity inversion feature in single width 10 bit wide data path configuration Figure 2 55 Receiver Polarity Inversion in Single Width Mode 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 Output from Deserializer Input to Word Aligner To Word Aligner rx _invpolarity HIGH ...

Page 82: ... the receiver polarity inversion feature in double width 20 bit wide data path configuration Figure 2 56 Receiver Polarity Inversion in Double Width Mode 1 0 1 0 0 0 0 0 1 1 Output from Deserializer Input to Word Aligner To Word Aligner rx _invpolarity HIGH 0 1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 ...

Page 83: ... width mode double width mode and automatic synchronization state machine mode The following sections explain each of the blocks in each mode of operation The word aligner cannot be bypassed and must be used However you can use the rx_enapatternalign port to set the word alignment to not align to the pattern Single Width Mode In single width mode there are three blocks active in the word aligner P...

Page 84: ...he specified standard or by user entered parameter rx_syncstatus rx_patterndetect Manual 7 and 10 bit alignment mode Alignment to detected pattern when allowed by the rx_enapatternalign signal rx_enapatternalign rx_syncstatus rx_patterndetect Manual 16 bit alignment mode Alignment to detected pattern when allowed by the rx_enapatternalign signal rx_enapatternalign rx_syncstatus rx_patterndetect Ma...

Page 85: ... For the 7 bit and 10 bit patterns the actual alignment pattern specified in the MegaWizard and its complement are checked For the 16 bit alignment pattern only the actual pattern is checked Table 2 19 shows the supported alignment patterns 1 In 8B 10B encoded data actual and complement pattern indicates positive and negative disparities Each bit in the rx_patterndetect and rx_syncstatus signal in...

Page 86: ...ord 10 Bit Pattern Mode In the 10 bit pattern detection mode use this mode with 8B 10B code the module matches the 10 bit alignment pattern you specified in your ALT2GXB custom megafunction variation with the data and its complement in the current word boundary Both positive and negative disparities are checked by the pattern checker in this mode For example if you specify a K28 5 b 0011111010 pat...

Page 87: ... the three MSBs allows the word aligner to resolve all three alignment patterns synchronized to it The word aligner places the boundary of the 7 bit pattern in the LSByte position with bit positions 0 7 The true and complement of the patterns is checked Use the rx_enapatternalign port to enable the 7 bit manual word alignment mode When the rx_enapatternalign signal is high the word aligner detects...

Page 88: ...le if an 8B 10B encoding scheme guarantees that the K28 5 code group is a unique pattern in the data stream the rx_enapatternalign port is held at a constant high If the alignment pattern can exist between word boundaries the rx_enapatternalign port must be controlled by the user logic in the PLD to avoid false word alignment For example assume that 8B 10B is used and a D19 1 b 110010 1001 charact...

Page 89: ... the current word boundary The alignment pattern is detected at time n 2 but it exists on a different boundary than the current locked boundary The bit orientation of the Stratix II GX device is LSB to MSB so the alignment pattern exists across time n 2 and n 3 refer to Figure 2 61 In this condition the rx_patterndetect remains low because the alignment pattern does not exist on the current word b...

Page 90: ...align signal If the byte boundary changes the rx_enapatternalign signal must be deasserted and reasserted to re enable the alignment circuit This feature is valuable in SONET SDH because the data is scrambled and not encoded The alignment pattern can potentially exist across byte boundaries and can trigger a false realignment In SONET SDH the byte boundary should be aligned and locked at the begin...

Page 91: ...ked The A1A2 alignment pattern appears again across word boundaries in during periods n 1 and n 2 The rx_enapatternalign signal is held high but the word aligner does not re align the byte boundary as it would in 10 bit manual alignment mode Instead the rx_syncstatus signal is asserted for one clock cycle to signify a re synchronization condition You must deassert and reassert the rx_enapatternali...

Page 92: ...eiver shifts the word boundary MSB to LSB one bit every parallel clock cycle The transceiver shifts the word boundary every time the bit slipping circuitry detects a rising edge of the rx_bitslip signal At each rising edge of the rx_bitslip signal the word boundary slips one bit The bit that arrives at the receiver first is skipped When the word boundary matches the alignment pattern you specified...

Page 93: ... or fall out of synchronization the synchronization state machine offers automatic detection of a valid number of alignment patterns and synchronization and detection of code group errors for automatically falling out of synchronization The synchronization state machine is available in the Basic single width mode only XAUI GIGE and PIPE modes For the XAUI GIGE and PIPE modes the number of alignmen...

Page 94: ...n program the number of bad code groups to fall out of synchronization You can program the number of good code groups to negate a bad code group You enter these values in the MegaWizard The rx_syncstatus port indicates the link status A high level indicates link synchronization is achieved a low level indicates that synchronization has not yet been achieved or that there were enough code group err...

Page 95: ...d code groups then when 3 consecutive good code groups are detected after a bad code group the effect of the bad code group on synchronization is negated This does not negate the bad code group that actually triggers the loss of synchronization To negate a loss of synchronization the protocol defined number of alignment patterns must be received Comma Detect if Data comma kcntr else kcntr kcntr Lo...

Page 96: ...utive ordered sets An ordered set starts with the K28 5 comma and can be followed by an odd number of valid data code groups Invalid code groups are not allowed during the reception of three ordered sets When code group synchronization is achieved the optional rx_syncstatus signal is asserted In PIPE mode lane synchronization is achieved when the word aligner sees 4 good K28 5 commas and 16 good c...

Page 97: ...ual and complement of the alignment patterns are checked and used with 8B 10B coding For the 8 bit 16 bit and 32 bit alignment patterns only the actual patterns are checked not the complements These patterns are used for scrambled coding or non encoded data 7 Bit Pattern Mode In the 7 bit pattern detection mode the pattern detector matches the seven least significant bits of the 10 bit alignment p...

Page 98: ...the pattern detector 16 Bit Pattern Mode You enable the two consecutive 8 bit characters A1A2 You specify the 16 bit alignment pattern which has the bit orientation of MSB LSB in the MegaWizard A1 represents the least significant byte which consists of bits 7 0 A2 represents the most significant byte which consists of bits 15 8 Therefore the alignment pattern is specified as A2 A1 in the MegaWizar...

Page 99: ... looks for the 7 bit alignment pattern you specified in the MegaWizard Plug In Manager in the incoming data stream The 7 bit alignment mode is useful because it can mask out the three most significant bits of the data which allows the word aligner to align to multiple alignment patterns For example in the 8B 10B encoded data a K28 5 b 0011111010 K28 1 b 0011111001 and K28 7 b 0011111000 share seve...

Page 100: ... aligner locks onto the first alignment pattern detected and places the detected pattern in the data stream on the LSByte position In this scenario rx_patterndetect is asserted to signify that the alignment pattern has been aligned The rx_syncstatus signal is also asserted to signify that the word boundary has been synchronized Manual 10 Bit Alignment Mode You can configure the word aligner to ali...

Page 101: ...ifferent boundaries Figure 2 68 shows an example of how the word aligner signals interact in 10 bit alignment mode For this example a K28 5 10 b0011111010 is specified as the alignment pattern The rx_enapatternalign signal is as a rising edge at time n alignment occurs whenever an alignment pattern exists in the pattern The rx_patterndetect signal is asserted for one clock cycle to signify that th...

Page 102: ...ected In this scenario the rx_patterndetect signal is asserted to signify that the alignment pattern has been aligned The rx_syncstatus signal is also asserted to signify that the word boundary has been synchronized Manual 20 bit Alignment Mode In the 20 bit alignment mode the pattern detector looks for the 20 bit alignment pattern K1K2 you specified in the MegaWizard in the incoming data stream T...

Page 103: ...er the first alignment pattern is detected and then after the rising edge of the rx_enapatternalign port If the byte boundary changes the rx_enapatternalign port must be deasserted and reasserted to enable the alignment circuit to search for and align to the next available alignment pattern On the rising edge of rx_enapatternalign the word aligner locks onto the first alignment pattern detected In...

Page 104: ...d data In single width mode the run length violation circuit detects up to a run length of 128 for an 8 bit deserialization factor or 160 for a 10 bit deserialization factor The settings are in increments of 4 or 5 for the 8 bit or 10 bit deserialization factors respectively In double width mode the run length violation circuit maximum run length detection is 512 with a run length increment of 8 a...

Page 105: ...word aligner get rewired to D 0 19 and D 0 9 respectively Flipping the parallel data using this feature allows the receiver to put out the correctly bit ordered data on the PLD interface in case of MSBit to LSBit transmission Since the receiver bit reversal is done at the output of the word aligner a dynamic bit reversal would also require a reversal of word alignment pattern As a result the Recei...

Page 106: ...r bit reversal feature in Basic single width 10 bit wide data path configuration Figure 2 69 Receiver Bit Reversal in Single Width Mode D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 Output of Word Aligner before RX bit reversal Output of Word Aligner after RX bit reversal RX Bit Reversal Enabled ...

Page 107: ...th 20 bit wide data path configuration Figure 2 70 Receiver Bit Reversal in Double Width Mode To Serializer RX Bit Reversal Enabled D 0 D 2 D 1 D 4 D 3 D 6 D 5 D 8 D 7 D 10 D 9 D 12 D 11 D 15 D 13 D 14 D 17 D 16 D 19 D 18 D 18 D 19 D 16 D 17 D 15 D 13 D 14 D 11 D 12 D 9 D 10 D 7 D 8 D 5 D 6 D 3 D 4 D 1 D 2 D 0 Output of Word Aligner before RX bit reversal Output of Word Aligner after RX bit revers...

Page 108: ...revbyteordwa swaps the 8 bit MSByte and LSByte of the 16 bit word at the output of the word aligner in the receiver data path This compensates for the erroneous swapping at the transmitter and hence corrects the data received by the downstream systems The rx_revbyteorderwa is a dynamic signal and may cause an initial disparity error at the receiver of an 8B 10B encoded link The downstream system m...

Page 109: ...ich relaxes the board design constraints Figure 2 72 shows lane skew at the receiver input and how the deskew circuitry uses the A code group to deskew the channels Figure 2 72 Lane Deskew With A Code Group Stratix II GX devices manage XAUI channel alignment with a dedicated deskew macro that consists of a 16 word deep FIFO buffer that is controlled by a XAUI deskew state machine The XAUI deskew s...

Page 110: ...e and Basic double width mode Figure 2 74 Rate Matcher reset sync_status FAIL SUDI sync_status OK SUDI A deskew_error SUDI A deskew_error SUDI A deskew_error SUDI A SUDI A SUDI A SUDI A deskew_error SUDI deskew_error SUDI deskew_error SUDI deskew_error SUDI deskew_error SUDI deskew_error SUDI deskew_error SUDI SUDI A LOSS_OF_ALIGNMENT align_status FAIL enable_deskew TRUE AUDI ALIGN_DETECT_1 enable...

Page 111: ... XAUI synchronization state machine achieves word alignment and channel alignment Until that point the rate matcher is not active read and write pointers do not move If the R code words are not received on all channels rate matching does not occur and may lead to over underflow conditions in the rate matching FIFO buffer If this situation occurs the data output of the receiver outputs a constant 9...

Page 112: ...luster of skip characters in PIPE mode only Figure 2 69 shows a PIPE mode rate matcher deletion of two skip characters Figure 2 75 PIPE Mode With Two Deletions One Per Cluster The rate matcher can perform skip character insertion one insertion per skip cluster in PIPE mode There is no limit on the consecutive number of skip characters allowed per skip cluster The Stratix II GX rate matcher in PIPE...

Page 113: ... in single width mode can delete any number of skip characters as necessary in a cluster as long as there are skip characters to delete There are no restrictions regarding deleting more than one skip character in a cluster of skip characters Figure 2 76 shows an example of a single width mode rate matcher deletion of two skip characters Although the skip characters are programmable the K28 0 contr...

Page 114: ...ter and the receiver The rate matcher looks for the skip ordered set which is usually a K28 5 comma followed by programmable neutral disparity skip characters for example K28 0 For general rate matching you can customize the SOS to support a variety of protocols including custom protocols The SOS must contain a valid control code group Kx y followed by any neutral disparity skip code group any Kx ...

Page 115: ... the double byte after the comma character if needed Figure 2 79 Insertion of Skip Characters in Double Width Mode 8B 10B Decoder The 8B 10B decoder Figure 2 80 is part of the Stratix II GX transceiver digital blocks and lies in the receiver path between the rate matcher and the byte deserializer blocks The 8B 10B decoder operates in two modes single width and double width modes and can be bypasse...

Page 116: ...and rxerrdectect Single Width Mode In single width mode the Stratix II GX 8B 10B decoder operates in a similar fashion as the Stratix GX 8B 10B decoder The highlighted data path in Figure 2 81 is active in the single width mode Figure 2 81 Active Data Path in Single Width Mode Note to Figure 2 81 1 Status signals include rx_ctrldetect rx_disperr and rxerrdectect 8B 10B Decoder MSByte datain 19 10 ...

Page 117: ...ontains an error This port is optional but if not in use there is no way to detect if a code received is valid or not The rx_errdetect signal goes high if a code received is an invalid code or if it has a disparity error If a code is received that is not part of the valid Dx y or Kx y list the rx_errdetect signal goes high This signal is aligned to the invalid code word received at the PLD logic a...

Page 118: ...by a K30 7 code 8 hFE on rx_dataout rx_ctrldetect In all other modes the code with incorrect disparity should be treated as an invalid code and ignored Figure 2 83 shows a case where the disparity is violated A K28 5 code has an 8 bit value of 8 hbc and a 10 bit value that depends on the disparity calculation at the point of the generation of the K28 5 code The 10 bit value is 10 b0011111010 10 h1...

Page 119: ...le waveform demonstrating the receipt of a K28 5 code BC ctrl The rx_ctrldetect 1 b1 is aligned with 8 hbc indicating that it is a control code The rest of the codes received are Dx y code groups Figure 2 84 Control Code Detection BC BC BC BC xx BC BC BC n n 1 n 2 n 3 n 4 n 5 n 6 n 7 clock rx_disperr rx_dataout 7 0 rx_errdetect Expected RD Code rx_ctrldetect RD Code Received rx_datain RD RD RD RD ...

Page 120: ...le width mode translates the 20 bit 2 10 bits encoded code into the 16 bit 2 8 bits equivalent data or control code The 20 bit upper and lower symbols received must be from the supported Dx y or Kx y list with the proper disparity or error flags asserted All 8B 10B control signals disparity error control detect and code error are pipelined with the data in the Stratix II GX receiver block and are ...

Page 121: ...n of the transceiver The lower bit indicates if the LSByte contains a code error the upper bit indicates if the MSByte contains a code error The value of the invalid code can vary and should be ignored Disparity Error Detector The 8B 10B decoder in double width mode forwards the current running disparity value from the LSByte decoder to the MSByte decoder to check the disparity of the symbol going...

Page 122: ... violated A K28 5 code has an 8 bit value of 8 hbc and a 10 bit value that depends on the disparity calculation at the point of the generation of the K28 5 code The 10 bit value is 10 b0011111010 10 h17c for RD or 10 b1100000101 10 h283 for RD This example uses double width mode and the 20 bit codes are split into two 10 bit codes for clarity The expected running disparity is indicated for each 10...

Page 123: ...he rx_ctrldetect 2 b1 is aligned with 8 hbc on the LSByte indicating that it is a control code The 8 hbc on the MSByte is a data not a control word The rest of the codes received are Dk y control codes Figure 2 88 Control Code Detection Reset The reset for the 8B 10B decoder block is derived from the receiver digital reset rx_digitalreset When rx_digitalreset is asserted the 8B 10B decoder block r...

Page 124: ...o Table 2 22 The PLD interface has a limit of 250 MHz so the byte deserializer is needed to widen the bus width at the PLD interface and reduce the interface speed For example at 6 375 Gbps the transceiver logic has a double byte wide data path that runs at 318 75 MHz in a 20 deserializer factor which is above the maximum PLD interface speed Figure 2 89 Byte Deserializer When using the byte deseri...

Page 125: ... the byte order to the expected pattern Byte Ordering The Stratix II GX device has a dedicated byte ordering circuit on each receiver to obtain a certain byte order on multiple lanes This circuit is used in conjunction with the byte deserializer block The byte deserializer doubles the number of lanes for each receiver If you use the single width mode the receiver output at the PLD interface 8 bits...

Page 126: ...position the byte ordering process is complete and the status signal rx_byteorderalignstatus asserts stays high If the alignment pattern is already in the LSByte position the byte ordering block detects this considers the byte ordering process complete and asserts the rx_byteorderalignstatus signal Byte ordering is not performed again even if the alignment byte exists in the data stream until the ...

Page 127: ...ignment based byte ordering PLD controlled byte ordering provides control to the user logic to restore correct byte order at the receiver When enabled an rx_enabyteord port is available at the PLD interface A rising edge on the rx_enabyteord port triggers the byte ordering block The byte ordering block looks for the user programmed byte ordering pattern in the data stream from the byte deserialize...

Page 128: ...ouble Width Mode After the first rising edge of the rx_enabyteord signal in Figure 2 95 the byte ordering block finds the byte ordering pattern A in the second most significant byte It adds two pad bytes PD to push the byte ordering pattern to the least significant byte position and asserts the rx_byteorderalignstatus signal After the second rising edge of the rx_enabyteord signal rx_byteorderalig...

Page 129: ...could choose the Start of Packet SOP byte as the byte ordering pattern if it is a unique control code say K28 0 In non 8B 10B scrambled data links it may be difficult to find a unique pattern since there is a possibility of the pattern appearing in the scrambled payload and causing the byte ordering block to add pad bytes incorrectly In such cases the instance at which the rx_enabyteord signal is ...

Page 130: ...ther the rate matcher is used or not In Basic mode the write port is clocked by the recovered clock from the CRU This clock is half the rate if the byte deserializer is used The read clock is clocked by the associated channel s recovered clock 1 The receiver phase compensation FIFO is always used and cannot be bypassed In four channel 4 and eight channel 8 bonding modes all the read pointers are d...

Page 131: ...PLD interface clocks available between the PLD logic and the transceiver blocks The 32 PLD interface clocks are divided equally between the top and bottom half of the device 16 PLD interface clocks for the top half of the device and 16 PLD interface clocks for the lower half The PLD interface clocks are used as the receiver and transmitter phase compensation FIFO clocks Figure 2 97 shows the PLD c...

Page 132: ...ransceiver block and channel configuration as listed in the above section There are options to route other PLD clocks to the tx_coreclk and rx_coreclk ports The non transceiver clocks that feed these ports are required to be frequency locked 0 ppm to the transceiver output clocks of the associated channel or transceiver block depending on the configuration The method of using this option is discus...

Page 133: ...other clock than the transceiver clock associated with that channel a PLD phase compensation must decouple the phase difference Figure 2 99 shows of TX and RX PLD phase compensation FIFOs decoupling the user logic from the transceiver RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 3 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 2 RX Phase Comp F...

Page 134: ...orts RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 3 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 2 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 1 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 0 PLD RX Phase Comp FIFO PLD RX Phase Comp FIFO PLD RX Phase Comp FIFO PLD RX Phase Comp FIFO PLD...

Page 135: ...hared Clock Group Setting is the safest assignment The Quartus II compiler will analyze the netlist during compilation to ensure TX channel members are derived from the same source The Quartus II software will give a fitting error for incompatible assignments The software cannot check for the output of the RX frequency locked to the driving clock as the exact frequency is dictated by the upstream ...

Page 136: ...ier value of 1 is also made to the rx_datain assignments A breakdown of the assignment in the assignment editor is shown in Table 2 23 Figure 2 100 shows the clocking configuration of the example 1 For 4 transceiver block configurations the coreclk_out can replace the tx_clkout 0 but the driver assignment still remains tx_dataout 0 Table 2 23 Assignment Editor To tx_dataout 0 Assignment name Strat...

Page 137: ...mpiler does not perform any checking on the clock source It is up to you to ensure that there is no frequency difference from the associated transceiver clock of the group and the driving clock to the tx_coreclk and rx_coreclk ports RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 3 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 2 RX Phase Comp FIF...

Page 138: ...oup identification The Stratix II GX 0 PPM Clock Group Setting is made to the TX or RX channel names A breakdown of the assignment in the assignment editor is shown in Table 2 24 The following are examples of clocking configurations that can use the 0PPM assignment All RX channels are configured the same and one recovered clock is feeding the rx_coreclk as shown in Figure 2 101 Though this example...

Page 139: ...a clock during analog reset of the driving channel If the reset state machine is clocked by the driver clock the reset state machine will hang and may not come out of reset All the RX channels will need to go through a digital reset in order to restore the phase compensation FIFO pointers Figure 2 101 rx_clkout 0 Feeding All Receivers of the Same Transceiver Block RX Phase Comp FIFO CRU RX TX Chan...

Page 140: ...r blocks as shown in Figure 2 102 The upstream device feeding the RX channels must be frequency locked to the tx_clkout used As with the RX channel example above it is important to note that powering down the transceiver block where the driving channel resides will flatline the tx_clkout All logic and the write ports of all the TX phase compensation FIFO will the driving clock feeds will flatline ...

Page 141: ...e frequency of the reference clock at the REFCLK pin be of the same frequency as the transceiver output clocks of the associated channels Any frequency difference yields corruption of data RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 3 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 2 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Bl...

Page 142: ... within a single transceiver block the 0PPM setting will also allow TX and or RX channel PCFIFOs of multiple transceiver blocks to be clocked by a common clock RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 3 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 2 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 1 RX Phase Comp F...

Page 143: ...resources are limited and determine the number of clocks that can be used between the PLD and transceiver blocks Tables 2 25 through 2 28 give the number of LRIO resources available for Stratix II GX devices with different numbers of transceiver blocks RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel 3 RX Phase Comp FIFO TX Phase Comp FIFO CRU RX TX TX CLK Div Block Channel...

Page 144: ...nections for Transceivers in 2SGX60E Clock Resource Transceiver Global Clock Regional Clock Bank13 8 Clock I O Bank14 8 Clock I O Bank15 8 Clock I O Region0 8 LRIO Clock v RCLK 20 27 v Region1 8 LRIO Clock v RCLK 20 27 v v Region2 8 LRIO Clock v RCLK 12 19 v v Region3 8 LRIO Clock v RCLK 12 19 v Table 2 27 Available Clocking Connections for Transceivers in 2SGX90F Part 1 of 2 Clock Resource Transc...

Page 145: ...Bank14 8 Clock I O Bank15 8 Clock I O Bank16 8 Clock I O Table 2 28 Available Clocking Connections for Transceivers in 2SGX130G Clock Resource Transceiver Global Clock Regional Clock Bank13 8 Clock I O Bank14 8 Clock I O Bank15 8 Clock I O Bank16 8 Clock I O Bank17 8 Clock I O Region0 8 LRIO Clock v RCLK 20 27 v Region1 8 LRIO Clock v RCLK 20 27 Region2 8 LRIO Clock v RCLK 12 19 v v Region3 8 LRIO...

Page 146: ...eclkout 1 Used only for four lane configurations Note to Table 2 29 1 Altera recommends using the REFCLK pin for pll_inclk The REFCLK pin uses inter transceiver line therefore there is no need to use the LRIO clock resource This usage helps with performance and resource Table 2 29 Clock Port List Part 2 of 2 Clock Name Maximum Number per Transceiver Block Notes Table 2 30 Example of LRIO Clock Res...

Page 147: ...rmation regarding the TX local divider blocks and the dual TXPLL configuration On the RX side it is possible to have up to four receiver channels to be of different data rates and configurations as long as there are enough PLD interface clocks to support the channels Since each receiver channel contains a dedicated RXPLL there are no data rate or configuration restrictions Bank15 Basic 4ch pll_inc...

Page 148: ...ine channels into a single transceiver block the transceiver block based control signals must be driven from the same source The following is a list of transceiver block based control signals gxb_powerdown reconfig_clk reconfig_togxb The gxb_powerdown signal of all the instances that are to be combined in a single transceiver block must be connected to a single point for example the same input pin...

Page 149: ...s they are within the same width mode for example if all operate in single width mode or if all operate in double width mode Mixing single width and double width modes is not allowed for TXPLL sharing Inst 1 gxb _powerdown Inclk rx_cruclk gxb _powerdown Inclk rx_cruclk gxb _powerdown Inclk rx_cruclk gxb _powerdown Inclk rx_cruclk refclk Powerdown Logic Inst 2 Inst 3 1 Duplex channel 1 Duplex chann...

Page 150: ...to set up the TXPLL for the highest data rate and use the dividers to drop the data rate down on the slower channels to 4 or 2 of the primary data rate Use the ALT2GXB MegaWizard to make your changes Non Basic protocol modes cannot share a TXPLL unless they are all of the same protocol and sub protocol 1 TXPLL sharing is restricted to the channels within a transceiver block Also the analog buffer ...

Page 151: ...bined Use the local dividers to achieve the desired data rate for each channel Because the goal is to have all four channels in a transceiver block driven off of a single TXPLL the reference clock will need to be from the same point either from a single dedicated REFCLK pin or from Though the example shows that there are two 4 Gbps channels configured in a single ALT2GXB instance duplicate channel...

Page 152: ... of TXPLL sharing compatible instances Figure 2 106 TXPLL Sharing Compatible Instances Ch 1 Data rate 4 Gbps TX Loc Div 1 Ch 0 Inst 1 TXPLL Primary Data rate 4 Gbps ALT2GXB Data rate 4 Gbps TX Loc Div 1 Ch 0 Inst 2 TXPLL Primary Data rate 4 Gbps ALT2GXB Data rate 2 Gbps TX Loc Div 2 Ch 0 Inst 3 TXPLL Primary Data rate 4 Gbps ALT2GXB Data rate 1 Gbps TX Loc Div 4 ...

Page 153: ...our assignments Since all the channels in this transceiver block are utilized the second TXPLL is not used However you can use the second dedicated REFCLK input to feed the IQ lines or the PLD logic if you do not use the first dedicated REFCLK to drive the IQ lines or PLD logic Figure 2 107 Resultant Transceiver Block Configuration After Combining Instances Transceiver Block Ch 1 Data rate 4 Gbps ...

Page 154: ...Figure 2 108 will not be able to share a single TXPLL due to incompatible primary data rates Since there are only two different primary data rates you can merge the four channels into a single transceiver block It is assumed that the channels sharing the same TXPLL will meet the requirements described in the above example For the channels not sharing the same TXPLL the PLL parameters may be differ...

Page 155: ...Figure 2 108 TXPLL Sharing Incompatible Instances Ch 1 Data rate 4 Gbps TX Loc Div 1 Ch 0 Inst 1 TXPLL Primary Data rate 4 Gbps ALT2GXB Data rate 4 Gbps TX Loc Div 1 Ch 0 Inst 2 TXPLL Primary Data rate 2 Gbps ALT2GXB Data rate 2 Gbps TX Loc Div 1 Ch 0 Inst 3 TXPLL Primary Data rate 2 Gbps ALT2GXB Data rate 1 Gbps TX Loc Div 2 ...

Page 156: ...bps two reference clocks will be needed 1 If the reference clock is driven from the PLD only one connection exists for each transceiver block Both TXPLLs in a transceiver block cannot be driven from separate PLD clock pins If the reference clock frequencies are the same it is possible to drive both TXPLLs in a transceiver block from a single PLD clock pin or the dedicated REFCLK pin Figure 2 109 R...

Page 157: ... each receiver channel can be configured from separate ALT2GXB instances or the entire group as long as all the RX channels are the same can be configured in one instance Combining RX and TX channels in a Transceiver Block You can combine duplex channels and or a mixture of TX and RX channel instances into a single transceiver block For combining the duplex channel configuration the TX rules and r...

Page 158: ...e PCS or PLD logic array Basic Single Width Mode with x4 Clocking In basic single width mode the ALT2GXB MegaWizard provides a 4 option under the Which subprotocol will you be using option If you select this option all four transmitter channels within the transceiver block are clocked by clocks generated from the central clock divider block refer to Transmitter Clocking Bonded Channels on page 2 2...

Page 159: ...imitations If one or more channels in a transceiver block are configured to Basic single width mode with 4 clocking option enabled the remaining channels in that transceiver block must either have the same configuration or must be unused All used channels within a transceiver block configured to this mode must also run at the same data rate All channels within the transceiver block configured to t...

Page 160: ... Bank 14 to provide the input reference clock In a design with 16 channels placed across Banks 13 14 15 and 16 use the REFCLK pins of either Bank 14 or 15 De asserting the tx_digitalreset signal of all used transceiver blocks simultaneously after pll_locked signal from all active transceiver blocks goes high Ch0 Ch1 Ch2 Ch3 Ch0 Ch1 Ch2 Ch3 Basic Single Width mode with x4 clocking option enabled Ba...

Page 161: ...hannel Skew Basic Double Width Mode Use Basic double width mode for custom protocols that are not part of the pre defined supported protocols for example PIPE With some restrictions the following PCS blocks are available Transmitter phase compensation FIFO buffer Transmitter byte serializer Inter transceiver block IQ clock Bank13 Four Channels in Basic x4 clocking mode pll_inclk pll_inclk Bank14 F...

Page 162: ...applications because it relies on synchronous single ended type signaling with a wide multi drop data bus refer to Figure 2 114 Clock and data trace matching is required with PCI PCI Express uses differential serial signaling with an embedded clock to enable an effective through put of 2 Gbps per link to circumvent the limitations of PCI PCI Express operates in 1 4 8 16 and 32 configurations and i...

Page 163: ...ode The PIPE mode has a separate reset sequence Refer to Reset Sequence for PIPE Mode on page 2 218 for more information f The equalizer DC gain value in the MegaWizard Plug In Manager for PIPE mode is set to a default value of 1 If the equalizer DC gain is controlled by the ALT2GXB_RECONFIG controller the rx_eqdcgain input to the ALT2GXB_RECONFIG controller should be tied to 01 to be PCI E compli...

Page 164: ...st training sequence consists of a K28 5 followed by three K28 1 code group If there is one code group error during the synchronization process resynchronization must be performed Comma Detect if Data comma kcntr else kcntr kcntr Loss of Sync Data Valid Data Comma Data valid kcntr 3 kcntr 3 Synchronized Data valid Data Valid Synchronized Error Detect if Data valid ecntr gcntr 0 else if gcntr 16 ec...

Page 165: ...e number of fast training ordered sets required by the receiver to obtain reliable bit and symbol lock 4 2 D2 0 Data rate identifier Bit 0 Reserved set to 0 Bit 1 1 generation 1 2 5 Gbps data rate supported Bit 2 7 Reserved set to 0 5 Bit 0 0 1 Bit 1 0 1 Bit 2 0 1 Bit 3 0 1 Bit 4 7 0 D0 0 D1 0 D2 0 D4 0 and D8 0 Training control Bit 0 Hot reset Bit 0 0 deassert Bit 0 1 assert Bit 1 Disable link Bi...

Page 166: ...training ordered sets required by the receiver to obtain reliable bit and symbol lock 4 2 D2 0 Data rate identifier Bit 0 Reserved set to 0 Bit 1 1 generation 1 2 5 Gbps data rate supported Bit 2 7 Reserved set to 0 5 Bit 0 0 1 Bit 1 0 1 Bit 2 0 1 Bit 3 0 1 Bit 4 7 0 D0 0 D1 0 D2 0 D4 0 and D8 0 Training control Bit 0 Hot reset Bit 0 0 deassert Bit 0 1 assert Bit 1 Disable link Bit 1 0 deassert Bi...

Page 167: ...r There is no limit on the consecutive number of skip characters allowed per skip cluster The Stratix II GX rate matcher in PIPE mode has FIFO buffer overflow and underflow protection In the event of a FIFO buffer overflow the rate matcher deletes any data after the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full In an underflow condition the rate matcher i...

Page 168: ...al controls whether the channel goes into loopback when the power state is in P0 or receiver detect when in P1 state This signal does not have any affect in any other power states The tx_forceelecidle signal governs when the transmitter goes into an Electrical Idle state The tx_forceelecidle signal is asserted in P0s and P1 states and deasserted in P0 state In P2 state under normal conditions the ...

Page 169: ...yer must know when a skip character was added or removed Altera recommends monitoring the number of skip characters received The transmitter should send three skip characters in a standard skip ordered set Table 2 35 Power States and Functions Allowed in Each Power State Power State tx_detectrxloopback tx_forceelecidle P0 0 normal mode 1 data path in loopback mode 0 Must be deasserted 1 Illegal mo...

Page 170: ...tant of the step voltage to detect the presence of the receiver at the far end Upon receiver detect the pipestatus port indicates if a receiver is detected or not There is some latency after asserting the tx_detectrxloopback signal before the receiver detection is indicated The tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the tx_detectrxloopback to ensure that ...

Page 171: ... PCI E specification fast training sequences FTS are used for bit and byte synchronization to transition from L0s state to L0 Stratix II GX P0s to P0 power states The PCI E base specification states that the required time period for this transaction be within 16 ns to 4 us Currently the default PIPE ALT2GXB settings do not meet these requirements Therefore Altera developed NTFS fast recovery IP NF...

Page 172: ...s self contained so no input output ports are available to access the soft IP The NFRI takes control of the rx_locktorefclk and rx_locktodata signals on the ALT2GXB transceiver and therefore avoids the delay of the PPM detector discussed in PIPE Mode Default Settings on page 2 160 1 If you select the rx_locktorefclk and rx_locktodata signals in the MegaWizard Plug In Manager the Enable fast recove...

Page 173: ...the tx_clkout To reset this logic use the same signal that connects to the tx_digitalreset port of the PCI Express PIPE ALT2GXB instance The NFRI_PLD_logic contains A state machine sequence to generate the pipeelecidle_PLD and pipedatavalid_PLD signals 4us_timer A user implemented timer in the PLD logic to count 4 us This timer represents the maximum time period to transition from P0s to P0 per th...

Page 174: ...er Ignore rx_signaldetect during this step 5 Wait for the 3 2us_timer to expire Ignore rx signaldetect during this step 6 If one FTS ordered set is received and the 4us_timer has NOT expired Set pipeelecidle_PLD to the pipeelecidle value that is forward the pipeelecidle value from the ALT2GXB to the user logic Assert pipedatavalid_PLD Reset and pause the 3 2us_timer and 4us_timer Return to Step 1 ...

Page 175: ... 4us_timer has expired Reset and pause the 3 2us_timer and 4us_timer Set the pipeelecidle_PLD to the pipeelecidle value that is forward the pipeelecidle value from the ALT2GXB to the user logic Set pipedatavalid_PLD to the pipedatavalid value that is forward the pipedatavalid value from the ALT2GXB to the user logic Return to Step 1 ...

Page 176: ...Start Wait for EIOS or falling edge of rx_signaldetect EIOS or falling edge detected Assert pipeeleidle_PLD De assert pipedatavalid_PLD Wait 250 ns and then wait until rx_signaldetect is asserted rx_signaldetect asserted Start 3 2 us and 4 us timers Wait for the 3 2 us timer to expire and ignore rx_signaldetect 3 2 us timer expires Assert rx_digitalreset for two parallel clock cycles 2 Wait for rx...

Page 177: ...he ALT2GXB MegaWizard Plug In Manager You can bypass the rate match FIFO in single lane 1 four lane 4 and eight lane 8 PIPE modes In normal PIPE mode the receiver blocks following the rate match FIFO are clocked by tx_clkout 1 mode or coreclkout 4 and 8 modes of the local port In low latency mode since the rate match FIFO is bypassed these receiver blocks are clocked by the recovered clocks of the...

Page 178: ...d A high value on the tx_rxdetectloop signal when the transceiver is in P1 power state will not force it to perform reverse parallel loopback Link Width Negotiation In normal multi lane 4 and 8 PIPE configuration the receiver phase compensation FIFO control signals for example write read enable are shared among all lanes within the link As a result all lanes are truly bonded and the lane lane skew...

Page 179: ...ndent Interface XGMII and XGMII to XGXS code group conversion macros For HiGig the Stratix II GX XAUI data rate protocol has been extended from 3 125 Gbps up to 3 75 Gbps For HiGig data rates select the XAUI protocol and type in the increased data rate The XAUI standard is an optional self managed interface that is inserted between the reconciliation sublayer and the PHY layer to transparently ext...

Page 180: ...channels 1 transmit clock 1 receive clock 4 transmitter control characters and 4 receive control characters for a total of a 74 pin wide interface XAUI consists of 4 differential transmitter channels and 4 differential receiver channels for a total of a 16 pin wide interface This reduction in pin count significantly simplifies the routing process in the layout design Figure 2 121 shows the relatio...

Page 181: ... reach of the XGMII and also reduces the interface pin count XAUI functions as a self managed interface because code group synchronization channel deskew and clock domain decoupling is handled with no upper layer support requirements This functionality is OSI Reference Model Layers Application Presentation Session Transport Network Data Link Physical PMA PMD Medium 10 Gb s XGMII XGMII MDI XAUI Opt...

Page 182: ... XGMII Character to PCS Code Group Mapping XGMII TXC XGMII TXD 1 PCS Code Group Description 0 00 through FF Dxx y Normal data transmission 1 07 K28 0 K28 3 or K28 5 Idle in I 1 07 K28 5 Idle in T 1 9C K28 4 Sequence 1 FB K27 7 Start 1 FD K29 7 Terminate 1 FE K30 7 Error 1 Other value Reserved XGMII character 1 Any other value K30 7 Deleted XGMII character Note to Table 2 38 1 Values in TXD column ...

Page 183: ...synchronization process specified in clause 48 of the IEEE P802 3ae standard which states that synchronization is achieved upon the reception of four K28 5 commas Each comma can be followed by any number of valid code groups Invalid code groups are not allowed during the synchronization stage When you configure Stratix II GX devices to the XAUI protocol the built in pattern detector word aligner a...

Page 184: ...UDI INVALID good_cgs 3 PUDI INVALID PUDI INVALID PUDI INVALID PUDI INVALID PUDI INVALID PUDI signal_detect n FAIL PUDI COMMA LOSS_OF_SYNC lane_sync_status n FAIL enable_cgalign TRUE SUDI COMMA_DETECT_1 enable_cgalign FALSE SUDI SYNC_ACQUIRED_1 lane_sync_status n OK SUDI SYNC_ACQUIRED_2 good_cgs 0 SUDI SYNC_ACQUIRED_3 good_cgs 0 SUDI SYNC_ACQUIRED_4 good_cgs 0 SUDI PUDI INVALID PUDI INVALID PUDI IN...

Page 185: ...atix II GX devices manage XAUI channel alignment with a dedicated deskew macro that consists of a 16 word deep FIFO buffer that is controlled by a XAUI deskew state machine The XAUI deskew state machine first looks for the A code group within each channel When the XAUI deskew state machine detects A in each channel the deskew FIFO buffer is enabled The deskew state machine now monitors the recepti...

Page 186: ...mode the controller begins to write data into the FIFO buffer whenever the rx_channelaligned signal is asserted Within the control logic there is a FIFO counter that keeps track of the read and write executions When the FIFO counter reaches a value of greater than nine the receivers delete the R code group reset sync_status FAIL SUDI sync_status OK SUDI A deskew_error SUDI A deskew_error SUDI A de...

Page 187: ...s the PCS code group to XGMII character mapping XGMII Character to PCS Code Group Mapping In XAUI mode the 8B 10B encoder in Stratix II GX devices is controlled by a global transmitter state machine that maps various 8 bit XGMII codes to 10 bit PCS code groups This state machine complies with the IEEE 802 3ae PCS transmit specification Figure 2 126 shows the PCS transmit source state diagram speci...

Page 188: ...d_sel 1 A_CNT 0 cod_sel 1 A_CNT 0 A_CNT 0 A_CNT 0 cod_sel 1 Q_det cod_sel 1 Q_det Q_det Q_det Q_det cod_set 1 A B B B A A B A cod_set 1 cod_set 1 B A PUDR SEND_K tx_code_group 39 0 K next_ifg A next_ifg A_CNT 0 next_ifg A_CNT 0 PUDR SEND_A tx_code_group 39 0 A next_ifg K SEND_Q tx_code_group 39 0 TQMSG Q_det K PUDR PUDR SEND_Q IF TX T THEN cvtx_terminate tx_code_group 39 0 ENCODE TX reset TX IDLE ...

Page 189: ... is divided into three sublayers the PCS the PMA and the physical medium dependent PMD layers GMII offers data rates up to 1000 Mbps at either half or full duplex modes Table 2 41 XGMII Character to PCS Code Group Mapping XGMII TXC XGMII TXD 1 PCS Code Group Description 0 00 through FF Dxx y Normal data transmission 1 07 K28 0 K28 3 or K28 5 Idle in I 1 07 K28 5 Idle in T 1 9C K28 4 Sequence 1 FB ...

Page 190: ...a independent interface that a variety of serial physical media can be connected to This layer handles the serialization and deserialization of the data The PMD sublayer defines actual physical attachment such as connectors for different media types Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transmitter Logic FPGA Logic Array TX Phase Compensation FIFO RX Phase Compen sat...

Page 191: ...a dedicated state machine governing their functions This state machine is only active in GIGE mode Table 2 42 shows the code groups used in the GIGE protocol If required for your design you must implement the remaining functions of the PCS auto negotiation collision detect and carrier detect in user logic or external circuits OSI Reference Model Layers Application Presentation Session Transport Ne...

Page 192: ...group Although you can have a number of synchronization patterns based on the synchronization rule three K28 5 followed by one Dx y code is the fastest synchronization pattern Once the synchronization is achieved the state machine considers a bad code group received cgbad if one of the following two conditions are met The incoming code group has a disparity error or a code group violation The inco...

Page 193: ...al_detect FAIL mr_loopback FALSE PUDI COMMA LOSS_OF_SYNC sync_status FAIL rx_even rx_even SUDI COMMA_DETECT_1 rx_even TRUE SUDI SYNC_ACQUIRED_2 rx_even rx_even SUDI good_cgs 0 SYNC_ACQUIRED_3 SYNC_ACQUIRED_4 cgbad cgbad cggood cgbad cgbad cggood cgbad cgbad cgbad SYNC_ACQUIRED_2A SYNC_ACQUIRED_3A SYNC_ACQUIRED_4A ACQUIRE_SYNC_1 SUDI COMMA_DETECT_2 SUDI 2 cggood good_cgs 3 cggood good_cgs 3 3 3 2 P...

Page 194: ...st pre configure the receiver with a K28 5 10 b0101111100 or 10 b1010000011 word align pattern ALIGN_PATTERN 0101111100 or ALIGN_PATTERN 1010000011 The ALIGN_PATTERN_LENGTH must be set to 10 even though a 7 bit comma string 7 b0011111 as a comma or 7 b1100000 as a comma is allowed as specified in IEEE 802 3 This 7 bit comma is located within the K28 1 K28 5 and K28 7 code groups Using a 10 bit K28...

Page 195: ...code groups If the receiver detects a bad code group or is reset the rx_syncstatus signal goes high then low and a K28 4 appears on the rx_outrx_dataout port Idle Generation In GIGE mode any Dx y following a K28 5 comma is replaced by the transmitter with either a D5 6 8 hc5 or a D16 2 8 h50 depending on the current running disparity except when the data following the K28 5 is D21 5 8 hb5 or D2 2 ...

Page 196: ... 2 is added or deleted based on how full or empty the rate matcher FIFO buffer is and if the current running disparity is negative The I2 order set contains two 10 bit code groups Two 10 bit groups 20 bits total are deleted or added at a time If the number of words in the FIFO buffer FIFO count is greater than nine the FIFO buffer stops writing when the I2 ordered set is detected Figure 2 134 If t...

Page 197: ...ber of Dx y sent as the transmitter before the synchronization sequence The last of the three automatically sent K28 5 and the first user sent Dx y are treated as one idle ordered set This can be a problem if there are an even number of Dx y transmitted before the start of the synchronization sequence Figure 2 136 shows an example of even numbers of Dx y between the last automatically sent K28 5 a...

Page 198: ...e support for SONET SDH protocol specific functions and electrical features for example alignment to A1A2 or A1A1A2A2 pattern Stratix II GX transceivers are designed to support the following three SONET SDH subprotocols OC 12 at 622 Mbps with 8 bit channel width OC 48 at 2488 32 Mbps with 16 bit channel width OC 96 at 4976 Mbps with 32 bit channel width SONET SDH Frame Structure Base OC 1 frames a...

Page 199: ...ytes are followed by twelve A2 bytes Similarly in an OC 48 backplane system forty eight A1 bytes are followed by forty eight A2 bytes In SONET SDH systems byte values of A1 and A2 are fixed as follows A1 11110110 or 8 hF6 A2 00101000 or 8 h28 OC 12 and OC 48 Data Paths OC 12 and OC 48 configurations have similar data paths as seen in Figures 2 138 and 2 139 The only difference is that OC 48 has a ...

Page 200: ...ver data path If required you should implement byte ordering logic in the PLD logic array in OC 96 configurations Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transmitter Logic FPGA Logic Array TX Phase Compensation FIFO RX Phase Compen sation FIFO Byte Serializer 8B 10B Encoder Serializer Clock Recovery Unit Word Aligner Deskew FIFO 8B 10B Decoder Byte De serializer Byte O...

Page 201: ... you must select appropriate word aligner settings in the MegaWizard Table 2 43 lists correct word aligner settings for each bit transmission order OC 12 and OC 48 Word Alignment SONET SDH mode uses manual word alignment as described in Manual SONET SDH Alignment Mode Two Consecutive 8 bit Characters A1A2 or Four Consecutive 8 bit Characters A1A1A2A2 on page 2 78 In OC 12 and OC 48 configurations ...

Page 202: ...utive 8 bit Characters A1A2 or Four Consecutive 8 bit Characters A1A1A2A2 on page 2 78 OC 96 Word Alignment In OC 96 configuration the word aligner is only allowed to align to a A1A1A2A2 pattern so input port rx_a1a2size is unavailable Barring this difference the OC 96 word alignment operation is similar to that of the OC 12 and OC 48 configurations OC 48 Byte Serializer and Deserializer The OC 48...

Page 203: ...iguration the byte ordering block is unavailable and ordering must be performed in the PLD logic array The byte ordering in an OC 48 configuration is automatic as explained in Word Alignment Based on Byte Ordering on page 2 114 In automatic mode the byte ordering block is triggered by the rising edge of the rx_syncstatus signal As soon as the byte ordering block sees the rising edge of the rx_sync...

Page 204: ...ation in OC 48 OIF CEI PHY Interface Mode The OIF CEI PHY Interface mode is intended to support two main protocols Common Electrical I O CEI 6G protocol defined by the Optical Internetworking Forum OIF at data rates between 4 976 Gbps and 6 375 Gbps Interlaken protocol at data rates between 3 135 Gbps and 6 375 Gbps Stratix II GX transceivers support a data rate between 3 135 Gbps and 6 375 Gbps i...

Page 205: ... block Otherwise clocks generated by the local clock divider in each channel clock the respective channel Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transmitter Logic FPGA Logic Array TX Phase Compensation FIFO RX Phase Compen sation FIFO Byte Serializer 8B 10B Encoder Serializer Clock Recovery Unit Word Aligner Deskew FIFO 8B 10B Decoder Byte De serializer Byte Ordering ...

Page 206: ...e configured in OIF CEI PHY Interface mode with this option enabled or must be unused All used channels within a transceiver block configured in OIF CEI PHY Interface mode with improved jitter clocking option enabled must also run at the same data rate Figures 2 144 and 2 145 show two examples each of legal and illegal transceiver placements with respect to the improved jitter clocking option in O...

Page 207: ... Ch 1 Ch 2 Ch 3 OIF CEI PHY Interface Mode with the low jitter option enabled Data Rate 5 Gbps OIF CEI PHY Interface Mode with the low jitter option enabled Data Rate 5 Gbps OIF CEI PHY Interface Mode with the low jitter option disabled OIF CEI PHY Interface Mode with the low jitter option disabled Unused Channel Unused Channel Serial RapidIO Serial RapidIO Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 ...

Page 208: ...I mode Figure 2 146 SDI Mode Data Path Table 2 45 shows ALT2GXB configurations supported by the Stratix II GX transceivers in SDI mode Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transmitter Logic FPGA Logic Array TX Phase Compensation FIFO RX Phase Compen sation FIFO Byte Serializer 8B 10B Encoder Serializer Clock Recovery Unit Word Aligner Deskew FIFO 8B 10B Decoder Byte...

Page 209: ... the byte deserializer 1 SDI receiver functions such as de scrambling framing and CRC checker must be implemented in the FPGA logic array Receiver Word Alignment Framing In SDI systems since the word alignment and framing happens after de scrambling the word aligner in the receiver data path is not useful Altera recommends driving the ALT2GXB rx_bitslip signal low to avoid the word aligner from in...

Page 210: ...s 4 Serial RapidIO link do not have lane alignment or deskew capability Figure 2 147 shows the ALT2GXB transceiver data path when configured in Serial RapidIO mode Figure 2 147 Serial RapidIO Mode Stratix II GX transceivers when configured in Serial RapidIO functional mode provide the following PCS and PMA functions 8B 10B encoding decoding Word alignment Lane Synchronization State Machine Clock r...

Page 211: ...chronization state machine to indicate synchronization when the receiver receives 127 K28 5 10 b0101111100 or 10 b1010000011 synchronization code groups without receiving an intermediate invalid code group Once synchronized the state machine indicates loss of synchronization when it detects three invalid code groups separated by less than 255 valid code groups or when it is reset Receiver synchron...

Page 212: ...erial RapidIO Mode CPRI Mode The common public radio interface CPRI specification defines a radio base station interface standard between the radio equipment control REC and the radio equipment RE Loss of Sync Data Comma Comma Detect if Data Comma kcntr else kcntr kcntr Synchronized Data valid kcntr 3 kcntr 127 Synchronized Error Detect if Data Valid ecntr gcntr 0 else if gcntr 255 ecntr gcntr 0 e...

Page 213: ...de Figure 2 149 ALT2GXB Transceiver Data Path in CPRI Mode Table 2 47 shows ALT2GXB configurations supported by the Stratix II GX transceivers in CPRI mode Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transmitter Logic FPGA Logic Array TX Phase Compensation FIFO RX Phase Compen sation FIFO Byte Serializer 8B 10B Encoder Serializer Clock Recovery Unit Word Aligner Deskew FIF...

Page 214: ...n use this programmability to implement the Loss of Signal LOS Loss of Frame Synchronization LOF and the Remote Alarm Indication RAI features in the FPGA logic array The synchronization status is reported on the rx_syncstatus port from the ALT2GXB The rx_syncstatus signal is driven high when the programmed conditions for synchronization state machine are met Otherwise it is driven low to indicate ...

Page 215: ...clocked by its own tx_clkout and rx_clkout for other modes as well The default transceiver configuration used to create the programming file sof or pof must be CPRI for the delay algorithm to take effect In CPRI mode you cannot group the tx_coreclk and or rx_coreclk ports of multiple channels and drive them using a common clock driver using the shared clock or 0 PPM clock group assignments Each CP...

Page 216: ... Figure 2 150 shows how to set 60 40 duty cycle constraints in TimeQuest Timing Analyzer for a CPRI 614 4 Mbps line rate configuration In the TimeQuest Analyzer window selecting the Report Clocks option lists all the tx_clkout and rx_clkout clocks in your design Select all clocks and adjust the falling edge timing appropriately for 60 40 duty cycle Figure 2 150 Setting Duty Cycle in TimeQuest Timi...

Page 217: ...ll functional modes except PCI Express PIPE Reverse serial loopback available in Basic mode with 8B 10B PCI Express PIPE reverse parallel loopback available in PCI Express protocol Reverse serial pre CDR loopback available in Basic mode with 8B 10BReverse serial loopback available in Basic mode with 8B 10B Parallel loopback available in Basic mode for BIST testing only Serial Loopback Figure 2 152...

Page 218: ...use it must be compliant with the PCI Express PIPE specification The data comes in from the rx_datain ports The receiver uses the CRU deserializer word aligner and rate matching FIFO buffer loops back to the transmitter serializer and then goes out the transmitter tx_dataout ports The data also goes to the PLD fabric on the receiver side to the tx_dataout port The deskew FIFO buffer is not enabled...

Page 219: ...e data is then fed through the CDR block in serial form directly to the tx_dataout ports in the transmitter block You can enable reverse serial loopback for all channels through the MegaWizard Any pre emphasis setting on the transmitter buffer is ignored in reverse serial loopback The data flows through the active blocks of the receiver and into the logic array Reverse serial loopback is often imp...

Page 220: ...test or verification use only to verify the signal being received after the gain and equalization improvements of the input buffer The signal at the output is not exactly what is received since the signal goes through the output buffer and the VOD is changed to the VOD setting level The pre emphasis settings have no effect Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transm...

Page 221: ...ching FIFO buffer are not available The 8B 10B encoder and decoder are used No dynamic control pin is available to enable or disable the loopback Test result pins rx_bistdone and rx_bisterr are available in this loopback mode When using parallel loopback the tx_dataout ports are active and the differential output voltage on the tx_dataout ports is based on the VOD settings Transmitter Digital Logi...

Page 222: ...cremental K28 0 K28 1 K28 2 K28 3 K28 4 K28 6 K28 7 K23 7 K30 7 K29 7 end of frame EOF and then repeats You must enable the 8B 10B encoder for proper operation No dynamic control pin is available to enable or disable the loopback Test result pins are Table 2 49 Available BIST Patterns in Double Width Mode PATTERN Word Aligner Alignment Pattern Byte Order Align Pattern Description Double Width Mode...

Page 223: ...on refer to Figure 2 157 The generators reside in the transmitter block and the verifier in the receiver block The generators can generate PRBS and incremental patterns The incremental pattern is available only in Parallel loopback mode The verifiers are only available for these data patterns The BIST blocks operate differently when in the single width mode and the double width mode The BIST modes...

Page 224: ... Table 2 50 shows the BIST patterns for single width mode Transmitter Digital Logic Receiver Digital Logic Analog Receiver and Transmitter Logic FPGA Logic Array BIST Incremental Generator TX Phase Compensation FIFO RX Phase Compen sation FIFO Byte Serializer 8B 10B Encoder Serializer BIST PRBS Verify Clock Recovery Unit Word Aligner Deskew FIFO 8B 10B Decoder Byte De serializer Byte Reorder BIST ...

Page 225: ...eterministic jitter using a time interval analyzer bit error rate tester or oscilloscope The PRBS verifier can provide a quick check through the non 8B 10B path of the transceiver block The PRBS verifier is active once the receiver channel is synchronized Set the alignment pattern to 10 h3FF for the 10 bit SERDES modes The verifier stops checking the patterns after receiving all the PRBS patterns ...

Page 226: ...oscilloscope The PRBS verifier provides a quick check through the non 8B 10B path of the transceiver block The PRBS verifier is active once the receiver channel is synchronized Set the alignment pattern to 20 h43040 for the 20 bit SERDES modes The PRBS verifier prevents the word aligner from aligning to a new pattern after the first five successfully verified words The verifier stops checking the ...

Page 227: ...LL enable signal All reset and enable signals are asynchronous tx_digitalreset The tx_digitalreset signal resets all digital logic in the transmitter including the XAUI transmit state machine the BIST PRBS generator and the BIST pattern generator This signal operates independently from the other reset signals The minimum pulse width is two parallel cycles rx_digitalreset The rx_digitalreset signal...

Page 228: ...al Table 2 52 shows the blocks affected by each reset and power down signal Table 2 52 Blocks Affected by Reset and Power Down Signals Part 1 of 2 Transceiver Blocks rx_digitalreset rx_analogreset tx_digitalreset gxb_powerdown Transmitter phase compensation FIFO buffer and byte serializer v v Transmitter 8B 10B encoder v v Transmitter serializer v Transmitter analog circuits v Transmitter PLLs v T...

Page 229: ... ns The tx_digitalreset and rx_analogreset signals can be deasserted after the driving PLL asserts its associated pll_locked signal The rx_digitalreset signal can be de asserted 4us after the rx_freqlocklocked signal goes high time between markers 6 and 7 Receiver XAUI state machine v v Receiver byte ordering block v v BIST verifiers v v Receiver analog circuits v Table 2 52 Blocks Affected by Res...

Page 230: ...mpliance testing phase because of receiving Electrical Idle Figure 2 161 shows the reset sequence for PIPE mode Figure 2 161 PIPE Mode Reset Sequence Initialization and PCI E Compliance Phase After the device is powered up any PCI E compliant device performs compliance testing During this phase all the transceiver reset signals gxb_powerdown tx_digitalreset rx_analogreset and rx_digitalreset are a...

Page 231: ...locked goes low until rx_digitalreset is deasserted The PLD logic should ignore the data during this time period the time period between markers 8 and 11 in Figure 2 161 1 Minimum T1 period is 100 ns Minimum T2 and T3 periods are 4 us T4 indicates two parallel receive clock cycles Rate Matcher FIFO Buffer Overflow and Underflow Condition During the normal operating phase the reset controller monit...

Page 232: ...ted you must assert tx_digitalreset rx_digitalreset and rx_analogreset signals appropriately for correct simulation behavior If the gxb_powerdown port is instantiated and other reset signals are not used you must assert the gxb_powerdown signal for at least one parallel clock cycle for correct simulation behavior In simulation you can de assert the rx_digitalreset immediately after rx_freqlocked s...

Page 233: ...Identifying Unconstrained Reset Ports To identify the unconstrained reset powerdown ports follow these steps 1 After compiling your design select the TimeQuest Timing Analyzer in the Tools drop down menu This opens up the Quartus II TimeQuest Timing Analyzer window PMA loopback Serial loopback Tri state 4 toggle Receiver 5 Reverse serial loopback Transmitter 4 Receiver Notes to Table 2 53 1 Either...

Page 234: ... port is driven by synchronous logic it will be listed in the Unconstrained Output Port Paths report 5 In the Unconstrained Input Port Paths and Unconstrained Output Port Paths reports the unconstrained reset powerdown ports of your ALT2GXB instances are listed under the To column Consider the design example in Figure 2 163 Figure 2 163 Example Design for TimeQuest Timing Analyzer Constraints In t...

Page 235: ...Altera Corporation 2 223 October 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX Transceiver Architecture Overview Figure 2 164 Unconstrained Input Port Paths ...

Page 236: ...t Timing Constraints You must add the reset powerdown port timing constraints either directly in the SDC file or through the TimeQuest Timing Analyzer GUI To add the timing constraints using the TimeQuest GUI follow these steps 1 Locate the reset powerdown ports in either the Unconstrained Input Port Paths or Unconstrained Output Port Paths report 2 Right click on the reset powerdown port in the T...

Page 237: ... in the Tasks pane of TimeQuest Timing Analyzer window 8 Execute Report Top Failing Paths by double clicking this option in the Tasks pane of the TimeQuest Timing Analyzer window 9 Assuming all other paths in your design meet timing one or more of the paths involving reset powerdown ports might report timing violations This is because the design is not able to meet the preliminary timing constrain...

Page 238: ...elay set_max_delay from get_keepers reset_seq_tx_rx_rx_cruclk_rx_clkout inst2 gxb_powerd own to get_ports PIPE_DataGen_Ch inst alt2gxb alt2gxb_component chann el_quad 0 cent_unit OBSERVABLEQUADRESET 4 000 Set Minimum Delay set_min_delay from get_keepers reset_seq_tx_rx_rx_cruclk_rx_clkout inst2 gxb_powerd own to get_ports PIPE_DataGen_Ch inst alt2gxb alt2gxb_component chann el_quad 0 cent_unit OBS...

Page 239: ...clkout inst2 gxb_powerd own to get_ports PIPE_DataGen_Ch inst alt2gxb alt2gxb_component chann el_quad 0 cent_unit OBSERVABLEQUADRESET 2 000 After modifying the SDC file and running the Quartus II Fitter the Update Timing Netlist option should be executed followed by Report Top Failing Paths If the gxb_powerdown port still shows in the failing paths modify the slack appropriately in the SDC file an...

Page 240: ...s in TimeQuest Timing Analyzer after running the Quartus II Fitter Set a maximum delay of 10 ns for all such ports in the SDC file For example if the rx_invpolarity signal is driven by the signal top_rx_invpolarity on an input pin the SDC file constraint for this port should be set as set_max_delay from get_ports top_rx_invpolarity to get_keepers xcvr_inst receive OBSERVABLEINVPOL 10 000 Table 2 5...

Page 241: ...mination resistor calibration block that calibrates all the termination resistors in the transceiver channels of the entire device Figure 2 167 Calibration Block PLL and Output Buffer Calibration Block Each Stratix II GX transceiver block contains a PLL and output buffer calibration circuit to counter the effects of PVT process voltage and temperature on the PLL and output buffer Each transceiver ...

Page 242: ...sed for the reference clock You can instantiate a calibration clock port in the MegaWizard to supply your own clock through the cal_blk_clk port The frequency range of the cal_blk_clk is 10 MHz to 125 MHz If there are no slow speed clocks available use a divide down circuit for example a ripple counter to divide the available clock to a frequency in that range The quality of the calibration clock ...

Page 243: ...Device Handbook SDI MegaCore Function User Guide Specifications Additional Information chapter in volume 2 of the Stratix II GX Handbook Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Document Revision History Table 2 55 shows the revision history for this chapter Table 2 55 Document Revision History Part 1 of 6 Date and Document Version Changes Made...

Page 244: ...asic Single Width Mode Basic Double Width Mode SONET SDH Mode Receiver Bit Reversal Pattern Detector Module Channel Clock Distribution Low Latency PIPE mode Synchronization Word Aligner TimeQuest Timing Analyzer Added Referenced Documents Serial Digital Interface SDI Mode Serial RapidIO Mode CPRI Mode DC Coupling Basic Single Width Mode with x4 Clocking Added Table 2 2 Minor text edits Table 2 55 ...

Page 245: ...Receiver Detect Native Modes introduction XAUI Mode Manual 7 bit Alignment Mode Manual 8 bit Alignment Mode Manual 10 Bit Alignment Mode Manual 16 Bit Alignment Mode Manual 20 bit Alignment Mode Manual 32 Bit Alignment Mode Figure 2 72 Figure 2 73 Updated Table 2 6 and Figure 2 62 Added the TimeQuest Timing Analyzer section Added Reverse Serial Pre CDR Loopback section February 2007 v4 0 Replaced ...

Page 246: ...erface Clock Resources section including Tables 2 21 through 2 26 Updated Tables 2 1 2 9 2 45 Updated content from Transmitter Modules through Byte Serializer Updated and moved PLD transceiver information to Receiver Phase Compensation FIFO Error Flag Sections modified Receiver Detect Reverse Serial Loopback Signal Threshold Detection Circuit Parallel Loopback Clock Synthesis Double Width Mode Int...

Page 247: ... bits 15 8 to bits 31 24 in the 32 Bit Pattern Mode section Changed rx_outrx_dataout to rx_dataout in the GIGE Receiver Synchronization section Added new note to the Dynamic Transmit Rate Switch and Dedicated Reference Clock Pin Specifications sections Changed VCCHTX to VCCH throughout the chapter Changed TX VCM to VCM throughout the chapter Changed VCC_H to VCCH throughout the chapter June 2006 v...

Page 248: ...Four Consecutive 8 bit Characters A1A1A2A2 section Updated Manual Alignment Modes section Updated Code Error Detect section Updated Disparity Error Detector section Added Reset Sequence for PIPE Mode section including Figures 2 119 and 2 120 Updated Dynamic Reconfiguration Setup for alt2gxb Instance section Updated Table 2 34 Updated tx_preemp_2t port description in Table 2 34 February 2006 v3 0 U...

Page 249: ... equalization settings during runtime the dynamic reconfiguration controller provides an option to dynamically control the adaptive equalization AEQ hardware present in each of the transceiver channels The AEQ hardware continuously tunes the receiver equalization settings based on the frequency content of the incoming signal The dynamic data rate switch feature on the transmitter is enabled throug...

Page 250: ...o control the configurable settings of the transceiver The dynamic reconfiguration controller is a soft IP which utilizes Stratix II GX device PLD resources It is optimized for minimal PLD resource usage Only one controller is allowed per transceiver block The dynamic reconfiguration controller does not have the capability to control multiple Stratix II GX devices or any off chip interface 1 The d...

Page 251: ... ALT2GXB_RECONFIG The following items are not supported as part of the dynamic reconfiguration feature Mode switch to and from any 4 and 8 configurations Not backward compatible with Stratix GX devices To and from PCI Express PIPE mode with NFRI IP Testability features pseudo random binary sequence PRBS and built in self test BIST logical_channel_address 7 0 reconfig_togxb 2 0 Address Translation ...

Page 252: ...nel number setting range is from 0 156 in multiples of 4 because the dynamic reconfiguration interface is per transceiver block This range of 0 156 is the logical channel address based purely on the number of possible ALT2GXB instances To better understand how logical addressing works consider the scenario of 20 separate transmit and receive instances of the ALT2GXB megafunction in a design and ho...

Page 253: ... into the same transceiver block only when multiple channels of the same data rate and data path configuration are controlled by one dynamic reconfiguration ALT2GXB_RECONFIG controller instance Channels connected to multiple ALT2GXB_RECONFIG controllers will not be merged Dynamic Reconfiguration Controller Interface The dynamic reconfiguration controller supports write and read transactions Figure...

Page 254: ...e_sel signal is 4 bits wide Encoding of the reconfig_mode_sel signal when the Adaptive Equalization control option is not selected is as follows reconfig_mode_sel 2 0 000 Reconfiguration of Analog controls The Analog controls feature has been enabled in the Quartus II software version 6 0 and later 001 Channel Reconfiguration 011 Dynamic Transmit rate switch 100 101 110 Channel and CMU PLL Reconfi...

Page 255: ...econfiguration controllers They are Single Dynamic Reconfiguration Controller one controller controlling all the instances of the ALT2GXB in a device When multiple instances of the ALT2GXB megafunction are controlled by a single ALT2GXB_RECONFIG controller the following rules should be followed for setting the What is the number of channels controlled by the controller option Each instance of the ...

Page 256: ...troller Table 3 2 describes the ports for the dynamic reconfiguration controller Table 3 2 Port List of the Dynamic Reconfiguration Controller ALT2GXB_RECONFIG Part 1 of 6 Port Name Input Output Description reconfig_clk Input Input reference clock for the dynamic reconfiguration controller The frequency range of this clock is 2 5 MHz to 50 MHz The assigned clock uses global resources by default Th...

Page 257: ...or the read transaction If data_valid is high the read back data is valid That is the current data on the output control signals after data_valid is asserted high is the valid data read out This signal is only enabled when at least one read control port is enabled When a read control port is enabled and a write transaction is finished the data_valid signal goes high and the busy signal goes low er...

Page 258: ...200 960 110 1400 N A 111 N A N A tx_preemp_0t 1 Input Optional pre emphasis control for pre tap for the transmit buffer It is 4 bits per channel This signal controls both pre emphasis positive and its inversion 0 represents 0 1 7 represents 7 to 1 9 15 represents 1 to 7 8 maps to 0 tx_preemp_1t 1 Input Optional pre emphasis control for first post tap for the transmit buffer It is 4 bits per channe...

Page 259: ...s out the value written by its input control signal The signal width of this output signal is the same as its corresponding input control signal rx_eqctrl_out Output Output signal to read the setting of equalization setting of the ALT2GXB instance The signal width of this output signal is the same as its corresponding input signal rx_eqdcgain_out Output Equalizer DC gain output signal This signal ...

Page 260: ...OF_CHANNELS parameter reconfig_address_out 5 0 Output This signal indicates the address out and that the address read out is the current address to be reconfigured by the ALT2GXB_RECONFIG megafunction during channel reconfiguration This signal is 5 bit wide in channel reconfiguration mode and 6 bit wide in channel and CMU PLL reconfiguration mode reconfig_address_en Output This port indicates the ...

Page 261: ...h two instances of an ALT2XGB configuration Instance1 with five transceiver channels and Instance2 with three transceiver channels rate_switch_out 1 0 Output This signal reads out the value that has written in for the rate switch of specified transmitter outputs This output port is only applicable when reconf_mode_sel is set to 011 The output value is listed below 00 Divide by 1 01 Divide by 2 10 ...

Page 262: ...l number option to 0 Three Channel Transceiver Instance In the ALT2GXB MegaWizard set the What is the number of channels option to 3 Enable the Analog controls option under the dynamic reconfiguration settings to dynamically change equalization values also enable the Enable equalizer settings option The output signal reconfig_fromgxb is transceiver block based so the number of bits for this instan...

Page 263: ...ut for VOD and equalization from all the options available in the MegaWizard Also note the analog control signal widths are for 12 channels since the above channel setting is 12 Control signals for unused channels 5 to 7 and channel 11 can be tied to logic low zero ground In this design scenario the VOD signal tx_vodctrl width is 36 bits 12 channel tx_vodctrl 2 0 tx_vodctrl 35 0 Tie tx_vodctrl 35 ...

Page 264: ...abled The following are the typical steps to setup the configuration Five Channel Transceiver Instance1 In the ALT2GXB MegaWizard set the What is the number of channels option to 5 along with other options in the ALT2GXB MegaWizard Enable the Analog controls option under the dynamic reconfiguration settings to dynamically change equalization values also enable the Enable equalizer settings option ...

Page 265: ...ls option to 3 Enable the Analog controls option under the dynamic reconfiguration settings to dynamically change equalization values also enable the Enable equalizer settings option The output signal reconfig_fromgxb is transceiver block based so the number of bits for this instance is one since the number of channels is three The input signal reconfig_togxb is a fixed width of three bits Set the...

Page 266: ...g ALT2GXB instance Figure 3 4 ALT2GXB_RECONFIG Modules with Two ALT2GXB Modules reconfig_clk reconfig_fromgxb read write reconfig_togxb 2 0 data_valid busy reconfig_fromgxb reconfig_fromgxb 1 0 tx_vodctrl 8 0 rx_eqctrl 11 0 ALT2GXB_RECONFIG reconfig_clk read write reconfig_togxb 2 0 data_valid busy tx_vodctrl 14 0 rx_eqctrl 19 0 rx_eqctrl_out 19 0 tx_vodctrl_out 14 0 reconfig_fromgxb 1 0 tx_vodctr...

Page 267: ... number of channels is one The input signal reconfig_togxb is a fixed width of three bits Set the option What is the starting channel number to 0 Instantiating Five Times Using the Above 1 Channel ALT2GXB Instantiate the ALT2GXB v file or the symbol file five times Note that after instantiating five times add the starting channel number parameter to the symbol file Change the parameter option to 4...

Page 268: ...control ports are enabled If you select the read control port the data_valid signal is enabled Reading and updating all the output control signals is part of the write transaction Therefore the data_valid signal is asserted only when the write transaction is finished busy signal is low and all the output control ports are updated with the new data When a write transaction is initiated and a set of...

Page 269: ...ion File mif also known as MIF that is generated by the Quartus II software when an ALT2GXB instance is compiled Refer to Channel Reconfiguration on page 3 30 for more information about the MIF The dynamic reconfiguration controller ignores a new 16 bit word if the previously initiated write transaction is not complete As explained above an on going or active write transaction is signified by the ...

Page 270: ...annel reconfiguration The following are status signals other than the busy signal reconfig_address_en This is an optional output signal The ALT2GXB_RECONFIG asserts this signal to indicate the change in value on the reconfig_address_out port This signal only gets asserted after the dynamic reconfiguration controller completes writing the 16 bit data reconfig_address_out 4 0 This is an optional out...

Page 271: ...he error signal for two reconfig_clk cycles 1 PMA controls read operation None of the analog PMA read output ports rx_eqctrl_out rx_eqdcgain_out tx_vodctrl_out tx_preemp_0t_out tx_preemp_1t_out and tx_preemp_2t_out are selected in the ALT2GXB_RECONFIG MegaWizard reconfig_mode_sel is set to 0 read signal is asserted 2 PMA controls write operation None of the analog PMA control write input ports rx_...

Page 272: ...e self recovery option When this option is selected the dynamic reconfiguration controller waits for a pre defined number of reconfig_clk cycles based on the operation selected If the busy signal does not go low within the pre defined number of clock cycles it asserts the error signal for two reconfig_clk cycles Example for Using Logical Channel Address to Perform Channel Reconfiguration The dynam...

Page 273: ... create five additional transceiver channels you will need the following defparam parameter settings for Verilog designs to change the starting channel number for the stamped instantiations defparam instantiation1 starting_channel_number 4 defparam instantiation2 starting_channel_number 8 defparam instantiation3 starting_channel_number 12 defparam instantiation4 starting_channel_number 16 defparam...

Page 274: ...the same transceiver block or in the other transceiver block For both these assignments the logical_channel_address value is 4 for instantiation1 Figure 3 6 Multiple Stampings of a Single Channel ALT2GXB Instantiation ALT2GXB Instantiations ALT2GXB_RECONFIG controller reconfig_from gxb 5 0 reconfig_ togxb 2 0 reconfig_fromgxb 0 reconfig_fromgxb 1 reconfig_fromgxb 4 Channel 0 Logical channel number...

Page 275: ...m instantiation1 starting_channel_number 4 defparam instantiation2 starting_channel_number 8 In the ALT2GXB_RECONFIG MegaWizard set the Number of channels controlled by the reconfig controller option to 12 Connect the reconfig_fromgxb 0 to 2 port of the ALT2GXB_RECONFIG instantiation to the reconfig_fromgxb ports of instantiation0 to instantiation2 respectively as shown in Figure 3 7 In this case ...

Page 276: ...figuration ALT2GXB Instantiations ALT2GXB_RECONFIG controller reconfig_from gxb 2 0 reconfig_ togxb 2 0 reconfig_fromgxb 0 reconfig_fromgxb 1 reconfig_fromgxb 2 Channel 0 Logical channel number 0 Channel 1 Logical channel number 1 Channel 2 Logical channel number 4 Channel 3 Logical channel number 5 Channel 4 Logical channel number 8 Channel 5 Logical channel number 9 reconfig _ clk reconfig _ add...

Page 277: ... read transaction assert the read signal The data on the output control ports is not valid until the data_valid signal is high The data_valid signal goes high when the entire selected output signals have valid read values Both read and write transactions are based on the reconfig_clk and are edge triggered Assert the write_all and read signal for one reconfig_clk cycle Figure 3 10 Read Transaction...

Page 278: ...w set of legal register bits into the ALT2GXB by the dynamic reconfiguration controller With this feature you can either reconfigure the data rate of a channel or functional mode including Basic mode with the custom mode enumeration CME features or a mix of data rates and functional modes The CME features are additional transceiver features introduced in Basic functional mode Some of the CME featu...

Page 279: ...c functional mode switched between a Basic mode to another Basic mode There is no limit to the number of mode switches in channel reconfiguration assuming transceiver and core clocking supports the transition Channel reconfiguration supports the following configurations of the physical transceiver channel Duplex Channels TX and RX TX Only RX Only Independent TX Independent RX in one physical chann...

Page 280: ...pin_af1_pin_af4 mif the Quartus II software automatically generates file name You can change the MIF name One design can have multiple MIFs no limit and one MIF can be used to reconfigure multiple channels These MIFs can be stored in on chip or off chip memory 1 If you do not specify pins for the tx_dataout and rx_datain for the transceiver channel the Quartus II software selects a channel and gen...

Page 281: ...orporation 3 33 October 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX Dynamic Reconfiguration 1 On the Assignments menu select Settings Figure 3 12 Figure 3 12 MIF Generation Step 1 Settings Option ...

Page 282: ...rporation Stratix II GX Device Handbook Volume 2 October 2007 Channel and PMA Controls Reconfiguration 2 Select Fitter settings then choose More Settings Figure 3 13 Figure 3 13 MIF Generation Step 2 Fitter Settings ...

Page 283: ...erated in the Assembler stage of the compilation process However for any change in the design or the above settings the Quartus II software runs through the fitter stage before starting the assembler stage As previously discussed the channel reconfiguration can be a data rate reconfiguration using two TX PLLs and local clock dividers or a functional mode reconfiguration or both To reconfigure a ch...

Page 284: ...face clocking is related to the parallel transmit and receive clocks tx_clkout and rx_clkout These clocks are used to parallel transmit data into and parallel receive data out of the transceiver Core clocking is needed in any channel reconfiguration Core clock assignments clock grouping assignment and 0 PPM assignments will override the core clocking set in the ALT2GXB instance The details related...

Page 285: ...n the CDR that yields the best performance refer to Figure 3 16 Figure 3 16 Receive Local Clock Divider Block To configure the local divider using the same TX PLL base setting use the following steps 1 Set the base setting on the CMU PLL use the fastest data rate that is intended to be reconfigured to 2 Set the local clock divider setting use the effective data rate for that configuration 3 Enable...

Page 286: ...guration 6 Repeat the previous 5 steps with the same TX PLL base setting and different local clock divider settings 7 Group core clocking 8 Lock down the pin assignments for the clocks and generate the MIFs for above instances Steps 1 and 2 are the only steps related to the local clock divider settings Step 4 is a mandatory step and is an important part of clocking in every channel reconfiguration...

Page 287: ...r more information 4 In Channel Internals option enable the use alternate reference clock Mode 2 option Set all the parameters related to alternate PLL protocols data rates bandwidth and clock frequency 5 Set the what is the logical reference index option refer to the Logical Reference Index 6 Set the core clocking options transmit and receive This is a mandatory step for every channel reconfigura...

Page 288: ...ing Basic mode at 2 5 Gbps In Basic mode the alternate PLL setup is the most flexible you can choose and set from the supported bandwidth options and input reference clock frequencies For example if the alternate PLL happens to be a protocol functional mode like PCI E or GIGE the alternate PLL related options will be automatically populated by the Quartus II software For more information about the...

Page 289: ... 5 selecting the What is the local reference clock index option controls the MUX that selects the high speed clocks from the two TX PLLs MUX that selects one of the two input reference clocks rx_cruclk or rx_cruclk_alt on the receive side For example consider a system switching from GIGE to SONET SDH and vice versa Since both protocols GIGE with 125 MHz input reference clock and SONET SDH OC48 wit...

Page 290: ...e clock input leg MuxSelect logical reference index In this case since the logical reference index is set to 0 represents the SONET SDH the TX PLL based on GIGE is routed to input1 of the clock MUX and the alternate PLL configured for SONET SDH is connected to input0 of the clock MUX In the GIGE MIF the clock MUX select value is set to 1 to choose the clock from the GIGE TX PLL Figures 3 20 and 3 ...

Page 291: ...e clock MUX select value is set to 0 to choose the clock from the SONET SDH TX PLL Figure 3 21 MUX Setting GIGE and SONET SDH Mode Logical Reference Clock Index 1 When two modes are configured to switch from one to another using two TX PLLs you have to carefully select the logical reference index In this case make sure the logical reference index that is set in one MIF is a complement in the secon...

Page 292: ...s Independent TX only configuration with another Independent RX only configuration in one physical channel To place an Independent TX configuration and an Independent RX configuration in one physical channel follow the steps below Perform the pin assignments accordingly Instruct the Quartus II software to merge or group the TX and RX register settings into one MIF There are constraints with the In...

Page 293: ...econfiguration Core clocking is the write and read clock options for the Transmit Phase Comp FIFO and the Receive Phase Comp FIFO respectively Core clocking can be further classified to Transmitter core clocking Receiver core clocking Transmitter Core Clocking Transmitter core clocking is the write clocking options for the Transmit Phase Comp FIFO The transmitter core clocking is used to write the...

Page 294: ...lock options The ALT2GXB MegaWizard provides two options only for the tx_clkout settings When you select the tx_clkout options ensure that the selected tx_clkout option is compatible for all the intended reconfiguration modes for the transceiver channel The tx_coreclk selection and clock grouping assignments Assignment editor overrides the tx_clkout settings set in the ALT2GXB MegaWizard Figure 3 ...

Page 295: ...al mode With the dynamic reconfiguration controller and using the channel reconfiguration feature all four channels switch to 1 5 Gbps and vice versa Option 1 is applicable in this case and saves clock resources Figure 3 24 Option 1 Channel Reconfiguration Transmit Core Clocking Option 2 Use Respective Channel Transmitter Core Clocks This option enables the Quartus II software to select the indivi...

Page 296: ...er core clocking is the read clocking options for the Receive Phase Comp FIFO The receiver core clocking is used to read the parallel data into the Receive Phase Comp FIFO from the PLD interface The possible transmit core clock options are rx_clkout the Quartus II software automatically routes to PLD and back into Phase Comp rx_coreclk user supplied input clock Dynamic reconfiguration supports bot...

Page 297: ...ion 1 Share a Single Transmitter Core Clock Between Receivers This option enables the Quartus II software to select channel 0 tx_clkout of a transceiver block and route it to all four receiver channels This option is typically set when a transceiver block all four channels is in Basic or Protocol mode with rate matching switches to another Basic or Protocol mode with rate matching Figure 3 27 show...

Page 298: ...n is used when the individual channels in a transceiver block have rate matching with different data rates switched to another Basic or Protocol mode with rate matching Figure 3 28 illustrates a setup which has to switch between the following modes TX1 RX1 Basic 1 Gbps with rate matching to Basic 2 Gbps with rate matching TX3 RX3 Basic 4 Gbps with rate matching to Basic 1 Gbps with rate matching T...

Page 299: ...clkout signal and route it to the same channel s receiver Typically this option is used when a channel is set up to switch from a Basic or Protocol mode with or without rate matching to another Basic or Protocol mode with or without rate matching Figure 3 29 illustrates a setup which intends to switch between the following modes TX1 RX1 GIGE to SONET SDH OC48 TX2 RX2 Basic 2 5 Gbps no rate matchin...

Page 300: ...core clocking has been explained in detail in the preceding sections This section discusses the PLD data path interface The PLD data path interface needs to be set up when dynamic reconfiguration involves the following Mode switches involving PLD data width changes Mode switches involving enabling and disabling of PCS blocks or features for example CME features in a transceiver channel In the ALT2...

Page 301: ...T2GXB megafunction Generate a MIF with the Channel internals option enabled but with a different set of PCS features same analog features configured in the ALT2GXB megafunction In this case the Use alternate reference clock option is not enabled since the reconfiguration did not involve any changes to the data rate that would require another TX PLL You can use the Channel internals option in conju...

Page 302: ...e potentially enabled through the ALT2GXB MegaWizard enabled through the Reconfig2 tab the Quartus II software will not restrict this selection In this case the software assumes you are planning to switch to and from a PCI E mode Figures 3 30 and 3 31 show the MegaWizard pages you use to select the channel internals and channel interface options If the Channel interface option is enabled the follo...

Page 303: ...Altera Corporation 3 55 October 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX Dynamic Reconfiguration Figure 3 30 ALT2GXB Reconfiguration Channel Interface Enabled ...

Page 304: ...e Description Transmit Signal Description Based on Stratix II GX Supported PLD Interface Widths 8 bit PLD Interface tx_datainfull 7 0 8 bit data tx_datain The following signals are used only in 8B 10B modes tx_datainfull 8 Control bit tx_ctrlenable tx_datainfull 9 Force disparity enable for tx_datainfull 7 0 non PIPE mode Transmitter force disparity Compliance PIPE tx_forcedisp in all modes except...

Page 305: ...datain MSByte The following signals are used only in 8B 10B modes Two Control Bits tx_ctrlenable tx_datainfull 8 tx_ctrlenable LSB and tx_datainfull 30 tx_ctrlenable MSB Force Disparity Enable For non PIPE tx_datainfull 9 tx_forcedisp LSB and tx_datainfull 31 tx_forcedisp MSB For PIPE tx_datainfull 9 tx_forcedispcompliance LSB and tx_datainfull 31 tx_forcedispcompliance MSB Force Disparity Value t...

Page 306: ...ainfull 41 tx_ctrlenable MSB Force Disparity Enable tx_forcedisp tx_datainfull 9 tx_forcedisp LSB and tx_datainfull 20 tx_datainfull 31 tx_datainfull 42 tx_forcedisp MSB Force Disparity Value tx_dispval tx_datainfull 10 tx_dispval LSB and tx_datainfull 21 tx_datainfull 32 tx_datainfull 43 tx_dispval MSB 40 bit PLD interface with PCS PMA set to 20 bits Four 10 bit Data tx_datain tx_datainfull 9 0 t...

Page 307: ...dataoutfull 10 rx_syncstatus rx_dataoutfull 11 Disparity error status signal It indicates disparity error detected in rx_dataoutfull 7 0 rx_disperr rx_dataoutfull 12 Pattern detect status signal rx_patterndetect rx_dataoutfull 13 Reserved rx_dataoutfull 14 Reserved rx_dataoutfull 14 13 PIPE PCI E mode 2 b00 data OK 2 b01 1 SKP deletion 2 b10 elastic buffer underflow if data is 0xFE else 1 SKP inse...

Page 308: ...42 rx_syncstatus MSB Two Receiver Disparity Error Bits rx_dataoutfull 11 rx_disperr LSB and rx_dataoutfull 43 rx_disperr MSB Two Receiver Pattern Detect Bits rx_dataoutfull 12 rx_patterndetect LSB and rx_dataoutfull 44 rx_patterndetect MSB rx_dataoutfull 13 and rx_dataoutfull 45 Reserved rx_dataoutfull 14 and rx_dataoutfull 46 Reserved Two 2 bit PIPE Status Bits rx_dataoutfull 14 13 rx_pipestatus ...

Page 309: ...utfull 44 rx_patterndetect MSB rx_dataoutfull 13 and rx_dataoutfull 45 Reserved rx_dataoutfull 14 and rx_dataoutfull 46 Reserved Two 2 bit PIPE Status Bits rx_dataoutfull 14 13 rx_pipestatus LSB and rx_dataoutfull 46 45 rx_pipestatus MSB PIPE PCI E mode 2 b00 data OK 2 b01 1 SKP deletion 2 b10 elastic buffer underflow if data is hexFE else 1 SKP insertion 2 b11 elastic buffer overflow rx_pipestatu...

Page 310: ...atterndetect MSB rx_dataoutfull 13 and rx_dataoutfull 29 Reserved rx_dataoutfull 14 and rx_dataoutfull 30 Reserved rx_dataoutfull 15 and rx_dataoutfull 31 Reserved 20 bit PLD interface with PCS PMA set to 10 bits Two 10 bit Data rx_dataoutfull 9 0 rx_dataout LSByte and rx_dataoutfull 41 32 rx_dataout MSByte Two Receiver Sync Status Bits rx_dataoutfull 10 rx_syncstatus LSB and rx_dataoutfull 42 rx_...

Page 311: ...tect Bits rx_dataoutfull 10 rx_syncstatus LSB and rx_dataoutfull 26 rx_dataoutfull 42 rx_dataoutfull 58 rx_syncstatus MSB Four Receiver Disparity Error Bits rx_dataoutfull 11 rx_disperr LSB rx_dataoutfull 27 rx_dataoutfull 43 rx_dataoutfull 59 rx_disperr MSB Four Receiver Pattern Detect Bits rx_dataoutfull 12 rx_patterndetect LSB rx_dataoutfull 28 rx_dataoutfull 44 rx_dataoutfull 60 rx_patterndete...

Page 312: ... Receiver Pattern Detect Bits rx_dataoutfull 12 rx_patterndetect LSB rx_dataoutfull 28 rx_dataoutfull 44 rx_dataoutfull 60 rx_patterndetect MSB 40 bit mode Four 10 bit Control Data Bits rx_dataout rx_dataoutfull 9 0 rx_dataout LSByte rx_dataoutfull 25 16 rx_dataoutfull 41 32 rx_dataoutfull 57 48 rx_dataout MSByte Four Receiver Sync Status Bits rx_dataoutfull 10 rx_syncstatus LSB rx_dataoutfull 26 ...

Page 313: ...te_switch_ctrl port 00 Divide by 1 01 Divide by 2 10 Divide by 4 11 not supported do not set this value The above values are written and based in the ALT2GXB_RECONFIG instance initiating a write transaction by pulsing the write_all signal This feature can be enabled through two other features the analog settings and the Channel Reconfiguration When two or more features are enabled the reconfig_mod...

Page 314: ... the dynamic reconfiguration controller Due to this asynchronous switching there may a few bit errors and transitions in the transceiver status signals Therefore perform a one time PMA control read or write transaction from the dynamic reconfiguration controller during system bringup initialization This operation sets the transceiver to listen to the registers written by the dynamic reconfiguratio...

Page 315: ...sider this additional recommendation If the channels are duplex and have individually switching modes using channel reconfiguration consider the following Reset controllers should be channel based The channel_reconfig_done signal can be used as a condition to reset the transmit and receive of the transceiver channel during and after channel reconfiguration Transmit digital resets tx_digitalreset a...

Page 316: ... 33 channel_reconfig_done assertion signifies that the ALT2GXB_RECONFIG controller finished the channel reconfiguration by shifting an entire MIF into an ALT2GXB channel If the channel reconfiguration is done in an RX only design assert the rx_analogreset signal and follow the reset sequence on the receiver side Figure 3 33 shows the receiver sequence Dynamic Rate Switching For a design using dyna...

Page 317: ...equires different PLD interface widths or additional control signals provided in the Reconfig2 tab select the Channel interface option 6 Select the appropriate clocking scheme in the Reconfig2 tab 7 Select the required additional control signals for the configuration in the Reconfig2 tab this is only enabled if the Channel interface option is selected MIF Generation 8 Create a top level design and...

Page 318: ...te the MIF The MIFs are generated for all the ALT2GXB configurations 1 This method requires attention when generating the MIF Please check the following The different ALT2GXB instantiations should have the appropriate logical reference clock index option values The clock inputs for each instance should be connected to the appropriate clock source When you generate the MIF use proper naming for the...

Page 319: ...e PLD to transmit and receive data between the transceiver and the PLD logic based on the transceiver configuration Figure 3 34 shows the design functional blocks to perform channel reconfiguration Reset Control Logic 14 Implement the reset control logic to handle the transceiver and the system resets Refer to Reset Recommendations on page 3 66 for more information Figure 3 34 Functional Blocks fo...

Page 320: ... These differences determine the selection of parameters in the ALT2GXB MegaWizard and the required PLD logic to configure a transceiver channel between these two modes Figure 3 35 shows the required functional blocks to perform channel reconfiguration Table 3 5 Differences Between GIGE and SONET SDH OC48 Number Functional Block GIGE SONET SDH OC48 1 PLD width 8 16 2 8B 10B enabled Yes No 3 Rate m...

Page 321: ...ts the steps to create the ALT2GXB_RECONFIG instance Section II Sets up the control logic for the ALT2GXB_RECONFIG controller Section III Logic to process the GIGE and SONET SDH data This logic is required due to the differences in the data interface widths and the clocking between the two modes shown in Table 3 5 Section IV Resets the control logic to control the transceiver and system resets Res...

Page 322: ...CONFIG instance Step 1 Generate the ALT2GXB Instantiation for GIGE Mode This example shows the ALT2GXB instantiation for one channel GIGE and SONET SDH mode 1 Set the protocol to GIGE mode in the first screen Select the following control and status signals rx_digitalreset tx_digitalreset rx_analogreset rx_pll_locked rx_freqlocked 2 Add the other required status signals f For a list of ALT2GXB sign...

Page 323: ...OC48 protocol The MUX values selected for the GIGE and SONET SDH OC48 modes should be different 1 For example if you select 1 for the What is the logical reference index option for the SONET SDH OC48 mode you should select 0 for GIGE mode If you select the same values for the two modes the transceiver behavior after reconfiguration becomes unpredictable 9 Select the Channel interface option Select...

Page 324: ...l only for the modes for which they are intended For example the rx_byteorderalignstatus signal is only meaningful in SONET SDH OC48 mode PLD logic should not use these signals for GIGE mode f For more information about the protocol specific ALT2GXB interface signals refer to Stratix II GX ALT2GXB Ports List on page 2 2 in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of ...

Page 325: ...e protocol mode you selected in the first page of the ALT2GXB MegaWizard the Quartus II software requires the GIGE clock source to be connected to pll_inclk and rx_cruclk inputs 2 Connect the cal_blk_clock input of the ALT2GXB instance to a clock source f Refer to the Stratix II GX ALT2GXB Ports List on page 2 2 in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stra...

Page 326: ...lected for GIGE mode should not be changed 3 In the Reconfig tab select the Channel internals and alternate reference clock options In the protocol section select GIGE Select the same input clock frequency selected in step 1 4 For the logical reference clock index option choose the complement of what you selected in step 10 5 Select the channel interface and complete the instantiation Step 5 Gener...

Page 327: ...it until the busy signal from the ALT2GXB_RECONFIG megafunction is low 4 Check whether the reconfig_address_out is less than 28 decimals 5 Wait for the data out from memory location 1 corresponding to the new reconfig_address_out becomes available at the reconfig_data port before asserting the write_all signal Figure 3 36 shows the various signal transitions during channel reconfiguration The ALT2...

Page 328: ... channel interface that created tx_datainfull 44 bits wide and rx_dataoutfull 64 bits wide was selected In addition the rx_byteorderalignstatus and the rx_a1a2size signals were selected The PLD logic should selectively use some of these signals based on whether the transceiver channel is configured in GIGE mode or SONET SDH OC48 mode Channel_reconfig_done 001 0 1800 Reconfig_mode_sel busy Reconfig...

Page 329: ...and SONET SDH OC48 modes Based on the configured protocol mode the receive side logic selects the appropriate data path Table 3 6 PLD Interface Signals GIGE and SONET SDH OC48 Modes Signal Name Description GIGE MODE tx_datainfull 7 0 8 bit unencoded data input to the transceiver channel tx_datainfull 8 tx_ctrlenable control signal K D rx_dataoutfull 7 0 8 bit unencoded data output from the transce...

Page 330: ...ta received during the reconfiguration process 1 For a PMA only configuration for example changing the VOD equalization DC gain or pre emphasis the transceiver channel or the datapath in the PLD logic does not require a reset after reconfiguration Reset is required only for channel reconfiguration or rate switch Simulation To simulate channel reconfiguration some simulation tools only allow ram or...

Page 331: ...des Section II Steps to Create the ALT2GXB_RECONFIG Instantiation Section III Sets Up Control Logic in the PLD for ALT2GXB_RECONFIG Section IV Resets Control Logic Section I Steps to Create the MIF for the Two Transceiver Modes 1 In the first page of the ALT2GXB MegaWizard complete the following Set Mode to Basic Select single width Set the channel width to 16 Set the number of channels to 1 Set t...

Page 332: ...on Section II Control Logic for the RECONFIG Controller Follow the same procedure as described in Example 1 Configuring a Transceiver Channel Between GIGE Mode and SONET SDH OC48 Mode on page 3 72 Section III Logic for the Basic Mode 1 and Basic Mode 2 Datapath Clock the data to the transceiver with the tx_clkout signal on the transmitter side for both configurations Similarly for the receive side...

Page 333: ...ghest data rate in this example is 4 25 Gbps Single width can be selected only up to 3 125 Gbps Set the channel width to 32 The lowest PLD frequency allowed in the Quartus II software is 25 MHz Therefore the transceiver runs at 1 125 Gbps with a 32 bit PLD interface The PLD clock frequency in this case is 26 5 MHz 1125 40 26 5 3 Set the input frequency to 106 25 MHz 4 In the Reconfig tab check the...

Page 334: ...by a single dynamic reconfiguration controller When you first perform channel reconfiguration on a transceiver channel rx_freqlocked and rx_clkout of all channels that are connected to the reconfiguration controller go to 0 for a few clock cycles This occurs because the receive PLLs in the simulation model require a relock when channel reconfiguration is enabled 1 This issue happens only in simula...

Page 335: ...ous protocols and data rates This section discusses the dynamic reconfiguration features introduced in Quartus II software version 7 1 Altera assumes you have prior knowledge about the dynamic reconfiguration controller architecture refer to Dynamic Reconfiguration Controller Architecture on page 3 2 the Stratix II GX transceiver architecture and the memory initialization file mif also known as MI...

Page 336: ...ration Note 1 Note to Figure 3 38 1 Supported from the Quartus II software version 6 1 Overview of Quartus II Software Version 7 1 Features for Dynamic Reconfiguration The Quartus II software version 7 1 provides the following enhancements to support dynamic reconfiguration Three additional features to dynamically reconfigure the transceiver channel and the TX PLLs TX PLL only reconfiguration Chan...

Page 337: ...s In the following sections the new dynamic reconfiguration features and the different software settings required to implement these features are discussed in detail Conventions Used Throughout this document the following conventions are used Channel and CMU PLL reconfiguration refers to the three dynamic reconfiguration features introduced in the Quartus II software version 7 1 Channel and TX PLL...

Page 338: ...y selecting the Enable Channel and Transmitter PLL Reconfiguration option in the Reconfig tab the Quartus II software version 7 1 allows a maximum of five possible sources available for input reference clocks Figure 3 39 shows the different clock sources that connect to the transceiver block Figure 3 39 Transceiver Block with Global Clock Line Connections These five clock inputs appear as a pll_in...

Page 339: ...ut for the two TX PLLs in a transceiver block refer to Figure 3 39 In a receiver only channel configuration the RX PLL of each channel in a transceiver block can be clocked by an independent global clock line But if you connect different clock input pins to the RX PLL in each channel you cannot reuse the MIFs between these two channels This constraint is explained further in Input Reference Clock ...

Page 340: ... clock frequency is 4 5 or 25 3 For functional modes with an data rate greater than 3 125 Gbps If the input clock frequency is greater than or equal to 100 MHz AND If the ratio of data rate to input clock frequency is 8 10 or 25 When you use the channel and CMU PLL reconfiguration feature you can dynamically reconfigure the TX PLLs and the RX PLL in a transceiver block from any of the five availab...

Page 341: ... 2 mentioned above In the Reconfig Clk 1 tab set the following values for clock source1 set the what is the reconfig protocol driven by clock1 option to Basic set the what is clock 1 input frequency option to 100 MHz select the use clock1 reference clock divider option this enables the Quartus II software to instantiate the refclk pre divider for clock source1 You can also use a dedicated refclk i...

Page 342: ...in bank 13 and the clock source is connected to the pll_inclk_rx_cruclk 0 port When the generated MIF is used in a channel in other transceiver blocks for example bank 14 the same clock source needs to be connected to the pll_inclk_rx_cruclk 0 port Figures 3 41 and 3 42 show the incorrect and correct order of input reference clocks respectively In Figure 3 41 the clocking is incorrect to reuse the...

Page 343: ...troller remaps the clock input multiplexer information in the MIF generated for instance1 to correspond to instance2 During this translation process it assumes that the same clock input is connected to the pll_inclk_rx_cruclk port Therefore the reconfig controller selects the clock multiplexer value for the IQ line or global clock network that connects to the clock input of instance1 If you want t...

Page 344: ...gure 3 43 Incorrect Clocking Scheme to Reuse MIF Figure 3 44 Correct Clocking Scheme for Reusing MIF clock source Stratix II GX Device ALT2GXB Instance 1 bank 13 ALT2GXB Instance 2 bank 14 refclk0 156 25 MHz pll_inclk_rx_ cruclk 0 pll_inclk_rx_ cruclk 0 156 25 MHz refclk0 two different clock pins clock source Stratix II GX Device ALT2GXB Instance 1 bank 13 ALT2GXB Instance 2 bank 14 refclk0 156 25...

Page 345: ... and 4 The identification numbers are indicated by A in Figure 3 45 Keep the identification numbering consistent for all the subsequent MIF configurations Provide the identification numbers indicated by B and C in Figure 3 45 Maintain a consistent protocol input reference clock frequencies and reference clock pre divider settings for all the MIF Set these options indicated by D E and F in Figure 3...

Page 346: ...the main and alternate TXPLLs This identification is referred to as the logical tx pll value This value provides a logical identification to the TX PLL that is associated with a transceiver channel without requiring the knowledge of its physical location In the ALT2GXB MegaWizard when you provide the main TXPLL with a logical tx pll value for example 0 the alternate TXPLL automatically takes the c...

Page 347: ...st significant bit MSB of the reconfig_mode_sel to 0 when you use any of the above mentioned values As with the channel reconfiguration feature the reconfig controller automatically increments the reconfig_address_out values to read the appropriate words from the MIF memory Table 3 10 shows the address values incremented by the reconfig controller for the different features Table 3 9 reconfig_mode...

Page 348: ...n the reconfig controller powers down the selected logical TX PLL until the new values are updated The power down feature is explained in TX PLL Powerdown on page 3 109 To illustrate the functional blocks that are reconfigured the following example is used This same example is used for the three reconfiguration features Consider that you have an ALT2GXB instantiation with the following default con...

Page 349: ...5 Gbps data using a 156 25 MHz reference clock Assume that the logical tx pll is set to 0 for the main TXPLL Rate matcher is enabled in the ALT2GXB megafunction The alternate TXPLL is configured to 2 5 Gbps using a 125 MHz reference clock Consider that the MIF is generated for mode1 and mode2 Details on the steps to generate the MIF are covered later in this section The intent of this example is t...

Page 350: ...ata rates In this case all these channels can listen to the same TX PLL Instead of using the Channel and TX PLL Reconfiguration option write 38 words for individual channels you can configure the TX PLL write 10 words once to a different data rate This in turn changes the transmit data rate of all the channels listening to this TX PLL This mode is also useful when combined with the channel reconfi...

Page 351: ...n using the mode1 MIF respectively 1 All the channels listening to the configured TX PLL are affected due to this reconfiguration Figure 3 48 Reconfigured Functional Blocks After TX PLL Only Reconfiguration Channel Reconfiguration with TX PLL Select This option reconfigures the channel and the logical TX PLL select multiplexer shown in Figure 3 49 that selects the clock output from one of the TX P...

Page 352: ...tion on page 3 100 refer to Figure 3 46 for conditions before reconfiguration Figure 3 49 shows the reconfigured functional blocks after the mode1 MIF write is completed Note that the TX PLLs are not reconfigured Since the new MIF has the same functional blocks as the original configuration there is no change in the functional blocks or the data rate in the transmit side after reconfiguration Note...

Page 353: ...port If this port is enabled the dynamic reconfig controller uses the value on the logical_tx_pll_sel port ONLY if the logical_tx_pll_sel_en port is set to 1 refer to Figure 3 50 The values on these two ports should be held at a constant logic level until reconfiguration is completed Table 3 11 shows the selected logical_tx_pll value under all the combinations of these two signals Figure 3 50 Effe...

Page 354: ...ical_tx_pll value of 1 Keep the logical_tx_pll_sel and logical_tx_pll_sel_en signals at a constant logic level until the reconfig controller asserts the channel_reconfig_done signal Figure 3 51 Signal Transitions of the logical_tx_pll_sel and logical_tx_pll_sel_en Ports enabled not enabled value on the logical_tx_pll_sel port not enabled not enabled logical tx pll value stored in the MIF Table 3 1...

Page 355: ...and setting the logical_tx_pll_sel to 1 during reconfiguration Figure 3 52 Reconfigured Functional Blocks Using logical_tx_pll_sel in Channel and TX PLL Mode TX PLL Reconfiguration Refer to Figure 3 46 for the channel configuration before the mode1 MIF is written Figure 3 53 shows that the logical TXPLL1 is configured to 6 25 Gbps The transmit channel still listens to the logical TXPLL0 and theref...

Page 356: ...econfigured by the mode1 MIF and the logical_tx_pll_sel set to 1 Note that in this case the TX PLL is not configured After the MIF is written the logical TX PLL multiplexer gets configured to select the logical TXPLL1 1 pll_inclk_rx_cruclk 1 pll_inclk_rx_cruclk 0 156 25 MHz 125 MHz Clock Multiplier Unit clock MUX clock MUX 5 Gbps LOGICAL TXPLL0 6 25 Gbps LOGICAL TXPLL1 Full Duplex Transceiver Chan...

Page 357: ...letes reconfiguring the selected TX PLL The ALT2GXB_RECONFIG megafunction does not provide any external ports to control the TX PLL power down If you reconfigure the main TXPLL the pll_locked signal goes low If you reconfigure the alternate TXPLL the pll_locked_alt signal gets deasserted Therefore after reconfiguring the transceiver wait for the pll_locked or pll_locked_alt signal from the ALT2GXB...

Page 358: ...s Altera recommends that you follow a proper reset sequence during and after CMU PLL reconfiguration Figure 3 55 shows the recommended reset sequence Figure 3 55 Reset Sequence During and After CMU PLL Reconfiguration 1 2 3 4 5 As shown in Figure 3 55 assert the tx_digitalreset rx_digitalreset and rx_analogreset when you initiate the CMU PLL reconfiguration MIF writes After the dynamic reconfigura...

Page 359: ...equirements The Quartus II software version 7 1 provides new assignments and settings to support the above mentioned channel and CMU PLL reconfiguration features MIF Generation for Channel and CMU PLL Reconfiguration To enable the Quartus II software version 7 1 to generate a MIF with 38 words complete the following steps 1 Go to the Assignments menu and select Settings then Fitter settings 2 Clic...

Page 360: ...L reconfiguration option Assignment setting Assignment Name Stratix II GX GXB TX PLL Reconfig group setting as shown in Figure 3 57 If you have more than one channel with the Channel and CMU PLL Reconfiguration feature enabled and if you assign them to different reconfig groups without pin assignments for the tx_dataout pins the Quartus II software automatically assigns these channels to different...

Page 361: ...t_ch1 Assignment Name Stratix II GX GXB TX PLL Reconfig group setting Value 0 ALT2GXB MegaWizard Settings This section discusses the enhancements in the ALT2GXB MegaWizard to support the channel and CMU PLL reconfiguration feature Reconfig Tab Settings When you enable the channel internals field you can select the Enable channel and Transmitter PLL option shown in Figure 3 58 This option allows yo...

Page 362: ... Clock Multiplier Unit CMU PLL Reconfiguration 1 When you select the Enable Channel and Transmitter PLL Reconfiguration option you cannot select the Use alternate reference clock option used in channel reconfiguration feature These two fields are mutually exclusive Figure 3 58 Reconfig Tab ...

Page 363: ... Reconfig Alt PLL Tab Reconfig Clks 1 Tab This tab provides options for the input reference clocks The first option what is the main PLL logical reference clock index provides the logical tx pll value for the main TXPLL If you have enabled the alternate TXPLL in the Reconfig Alt PLL tab the ALT2GXB MegaWizard automatically selects the logical tx pll value of the main TXPLL as the complement of the...

Page 364: ... the selected input clock source for the Transmitter PLL and Receiver PLL and What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL options are used to select the input clocks for the main and alternate TXPLLs as well as the RX PLLs The What is the reconfig protocol driven by clock 0 and What is clock 0 input frequency options provide the protocol and clock fre...

Page 365: ...ated refclks on page 3 92 the Quartus II software automatically instantiates the refclk pre divider for the corresponding clock input For other clock inputs you should determine whether the clock input frequency and the data rate meets one of the conditions specified in Using Dedicated refclks on page 3 92 Example of a Condition to Select this Option Assume that you are using a clock input with a ...

Page 366: ...X Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about other ALT2GXB MegaWizard settings ALT2GXB RECONFIG Tab Settings The Quartus II software version 7 1 has the following enhancements in the ports values option in the ALT2GXB_RECONFIG MegaWizard reconfig_mode_sel The ALT2GXB_RECONFIG MegaWizard has new reconfig_mode_sel values to suppor...

Page 367: ...is port in the Channel and TX PLL Reconfiguration tab If this port is selected the ALT2GXB_RECONFIG block registers the value on the logical_tx_pll_sel only if the logical_tx_pll_sel_en is asserted Figure 3 62 shows the Channel and TX PLL reconfiguration tab in the ALT2GXB_RECONFIG MegaWizard in the Quartus II software version 7 1 Figure 3 62 ALT2GXB RECONFIG Tab The functionality of all other sig...

Page 368: ...uplex or TX only configuration that has a main and alternate TXPLL If you want to place other channels in the same transceiver bank the other channels should also have a main and alternate TXPLL option to merge successfully For example consider that you create the following instantiation Instantiation1 one full duplex channel with the main TXPLL assume a logical_tx_pll value of 0 configured to 6 2...

Page 369: ... PLL explained in Clocking Enhancements and Requirements on page 3 90 If you merge a transmit only and a receive only configuration the Quartus II software allows you to provide separate clock inputs for the TX PLL and RX PLL you can connect the pll_inclk_rx_cruclk port of the two instances to two different clock source When you merge the transmit only and receive only configurations you should ad...

Page 370: ...d to FC 4G protocol at system power up FC 4G uses Basic mode FC 4G and FC 2G refer to the fibre channel protocol at 4 25 Gbps and 2 125 Gbps data rate respectively Table 3 12 shows the different parameters and ALT2GXB functional blocks for these three protocols Table 3 12 Differences in Functional Blocks Between GIGE Fibre Channel and SONET SDH OC48 Note 1 Parameters Fibre Channel Basic Mode 4 25 ...

Page 371: ...cking and TX PLL connections only for CH0 and CH1 CH2 CH3 CH4 CH5 have the same configuration To simplify the illustration only the transmit channels of CH0 and CH1 and the TX PLL connections are shown If you create three MIFs for FC 4G GIGE and SONET SDH OC48 for one TX PLL you can reuse the MIF in the other TX PLL using the logical_tx_pll_sel port in the dynamic reconfig controller This means th...

Page 372: ...eps to Create the MIF Section IV Reset Control Logic and User Logic Section V Top Level Design and SRAM Object File sof Generation Section I ALT2GXB MegaWizard Settings for the Three Protocols Tables 3 13 3 14 and 3 15 list the MegaWizard settings for each of the three protocols pll_inclk_rx_cruclk 2 pll_inclk_rx_cruclk 1 pll_inclk_rx_cruclk 0 77 76 MHz 125 MHz 106 25 MHz clock MUX clock MUX 4 25 ...

Page 373: ...own if required TX Analog Tab Setting select the appropriate settings based on your requirements Reconfig Tab Settings select channel interface This is required since the three protocols require different PLD widths refer to Table 3 12 select channel internals and enable channel and transmitter PLL reconfiguration Reconfig Alt PLL Tab Setting In this example design you are using only two channels ...

Page 374: ... use respective core clocks since you clock the receive parallel date with tx_clkout for the GIGE protocol and rx_clkout for the other two protocols Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for more information about these options how should the transmitters be clocked use the respective channel transmitter core clocks ch...

Page 375: ...hat is the main PLL logical reference clock index 0 Note Use this setting because you intend to generate the MIF with a logical tx pll value of 0 Refer to How Many MIFs do I Require on page 3 123 how many input clocks 3 77 76 MHz 125 MHz and 106 25 MHz what is the select input clock source for transmitter and receiver PLL 1 what is the reconfig protocol driven by clock0 BASIC what is clock0 input ...

Page 376: ...alreset and rxanalogreset ports PLL Ports RX Analog Cal Blk TX Analog Reconfig Tab Settings set the same settings as the FC 4G ALT2GXB instance mentioned in Tables 3 13 Reconfig Alt PLL Tab Setting no selection required Reconfig Clks 1 Tab Settings what is the main PLL logical reference clock index 0 how many input clocks 3 77 76 MHz 125 MHz and 106 25 MHz what is the select input clock source for...

Page 377: ...LT2GXB_RECONFIG MegaWizard Instantiation The following are settings for the ALT2GXB_RECONFIG MegaWizard Set the What is the number of channels controlled by the reconfig controller option to 24 In this design you have six instantiations for six channels The starting channel numbers for each of these instantiations should be a multiple of four Each of these ALT2GXB instantiation has a reconfig_from...

Page 378: ...SONET SDH OC48 protocol Connect the pll_inclk_rx_cruclk ports to the following clock source a pll_inclk_rx_cruclk 0 106 25 MHz Assume refclk0 of transceiver bank 13 b pll_inclk_rx_cruclk 1 125 MHz Assume refclk0 of transceiver bank 14 c pll_inclk_rx_cruclk 2 77 76 MHz Assume refclk0 of transceiver bank 15 4 For this example design assume that the three clock inputs are provided from the dedicated ...

Page 379: ...eration Follow these steps to generate a SRAM object file 1 Instantiate the six ALT2GXB channels in the top level design That is stamp the FC 4G instance created for logical_tx_pll value 0 three times for CH0 CH2 and CH4 2 Similarly stamp the instance created for logical_tx_pll value 1 for CH1 CH3 and CH5 3 Add the reset and user logic and connect the signals In the assignment editor use the Strat...

Page 380: ...l need four MIFs for this design You can generate the MIFs for one TX PLL and use the logical_tx_pll_sel in the reconfig controller to write the MIF contents into the second TX PLL Assume that the TX PLL configured for FC 4G data rate is assigned a logical tx pll value of 0 This means that the other TX PLL configured for GIGE and SONET SDH pll_inclk_rx_cruclk 2 pll_inclk_rx_cruclk 1 pll_inclk_rx_c...

Page 381: ...on I ALT2GXB MegaWizard Settings for the Three Protocols In this section only the ALT2GXB MegaWizard settings relevant to the channel and CMU PLL reconfiguration feature are discussed in Tables 3 17 through 3 20 Refer to Tables 3 13 3 14 and 3 15 for the tab settings that are not specified in this section Table 3 16 MIF File for the Four Configurations Number MIF logical tx pll Value 1 FC 4G 0 2 F...

Page 382: ...channel internals and enable channel and transmitter PLL reconfiguration Reconfig Alt PLL Tab Setting what is the alternate PLL reference clock index 1 you used a logical tx pll value of 0 for FC 4G Therefore this alternate index for example GIGE should be set to 1 protocol GIGE data rate 1 25 Gbps clock frequency 125 MHz Reconfig Clks 1 and Reconfig2 Tab Settings use the same clock order as the p...

Page 383: ... Reconfig Alt PLL Tab Setting what is the alternate PLL reference clock index 0 You used a logical tx pll value of 1 for GIGE Therefore the alternate index for FC 4G should be set to 0 protocol BASIC data rate 4 25 Gbps clock frequency 106 25 MHz Reconfig Clks 1 and Reconfig2 Tab Settings use the same clock order as the previous example Refer to Table 3 13 Table 3 20 FC 2G Protocol Settings Part 1...

Page 384: ...uration Follow the same procedure as mentioned in MIF Generation for Channel and CMU PLL Reconfiguration on page 3 111 to create your MIFs In the top level design assign the Stratix II GX GXB TX PLL Reconfig group setting and assign the same reconfig group to the three channels If you would like to reconfigure CH0 to SONET SDH OC48 mode use the following steps 1 In the MegaWizard instantiation set...

Page 385: ... Stratix II GX device to continuously tune the receiver equalization settings based on the frequency content of the incoming signal Five equalizer filters are tuned during this adaptive equalization process The user logic can dynamically control the AEQ hardware through the dynamic reconfiguration controller This section explains the method to enable different options to control the AEQ hardware A...

Page 386: ...peak to peak The Quartus II software does not check for this requirement AEQ is supported only in device speed grades C3 C4 or I4 Enabling the AEQ Hardware The AEQ hardware is available for each transceiver channel in the Stratix II GX device To enable the AEQ hardware select the Enable adaptive equalizer control option in the Reconfig page of the ALT2GXB MegaWizard plug in Manager Figure 3 66 Tab...

Page 387: ...romgxb aeq_togxb fixedclk The aeq_fromgxb and aeq_togxb ports provide the interface between the transceiver channel ALT2GXB and the dynamic reconfiguration controller ALT2GXB_RECONFIG For each channel the width of the aeq_fromgxb and aeq_togxb ports are 6 bits and 4 bits respectively If you have multiple transceiver instances connect the least significant byte of the aeq_togxb 3 0 and aeq_fromgxb ...

Page 388: ...xedclk port should be between 2 5 MHz and 125 MHz To save clock routing resources you can use the same clock pin to provide input clocks for the fixedclk and reconfig_clk ports 1 When the transceiver channel is configured for PCI Express PIPE protocol the fixedclk is used to operate the receiver detect circuitry In this protocol mode fixedclk requires a fixed 125 MHz input clock frequency The AEQ ...

Page 389: ... the ALT2GXB_RECONFIG MegaWizard page with different AEQ options Figure 3 68 ALT2GXB_RECONFIG with Different Adaptive Equalization Control Options Controlling the AEQ Hardware The ALT2GXB_RECONFIG provides different options to start and power down the adaptive equalization hardware You can select these options by setting different values in the reconfig_mode_sel port To use these options set the r...

Page 390: ...e 3 69 Figure 3 69 AEQ Write Timing Diagram on a Single Channel When the write_all signal is asserted the dynamic reconfiguration controller writes the initialization and control values into the transceiver registers and initiates the adaptive equalization process During this initialization process the dynamic reconfiguration controller powers down the receiver buffer This results in transient bit...

Page 391: ... Write Timing Diagram on All Active Channels The dynamic reconfiguration controller initiates the write transaction for all the active channels starting with the lowest logical channel that has the AEQ feature enabled For example assume that you have three channels connected to a dynamic reconfiguration controller with logical address values of 0 4 and 8 respectively If the logical channels 4 and ...

Page 392: ...ng down the AEQ hardware the ALT2GXB_RECONFIG reads the adaptive equalization settings translates them to the nearest available manual equalization setting and automatically writes the translated manual equalization settings into the transceiver channel To read the translated manual equalization values perform a read operation using the PMA controls option The translated manual equalization values...

Page 393: ...tion setting Power Down for All Channels This option provides the flexibility to power down the AEQ hardware in all the active channels connected to the same dynamic reconfiguration controller The ALT2GXB_RECONFIG performs the translation as explained in Power Down Options on page 3 144 The dynamic reconfiguration controller powers down the AEQ hardware on all the active channels starting with the...

Page 394: ... The number of reconfig_clk cycles that the dynamic reconfiguration controller takes is approximately 700 times the number of active channels connected to the dynamic reconfiguration controller During the power down process there may be bit errors on the receiver output data for few receive parallel clock cycles In addition to controlling the AEQ hardware ALT2GXB_RECONFIG supports multiple feature...

Page 395: ...age 3 120 In addition to the above requirements when you enable the adaptive equalization option in the ALT2GXB MegaWizard for one transceiver instance the Quartus II software requires that you enable this option in the other channels to merge them in the same transceiver block Summary Using the dynamic reconfiguration feature you can reconfigure the analog controls data rates and protocols of the...

Page 396: ...ted Reconfig Clks 1 Tab Channel and PMA Controls Reconfiguration Example 3 Updated Figure 3 1 Figure 3 2 Figure 3 19 Figure 3 30 Figure 3 31 Figure 3 45 Figure 3 58 Figure 3 59 Figure 3 60 Figure 3 62 Updated Table 3 2 Added the Referenced Documents section Minor text edits August 2007 v1 0 Moved the Introduction section from the Stratix II GX Architecture Overview chapter to this chapter Updated ...

Page 397: ...g methods Choose the MegaWizard Plug In Manager command Tools menu When working in the Block Editor click MegaWizard Plug In Manager in the Symbol dialog box Edit menu Start the stand alone version of the MegaWizard Plug In Manager by typing the following command at the command prompt qmegawiz The ALT2GXB MegaWizard Plug In Manager allows you to configure one or more transceiver channels It also a...

Page 398: ...ager Select the Stratix II GX device as the device family Figure 4 2 MegaWizard Plug In Manager Page 2 Basic Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for Basic mode The MegaWizard Plug In Manager provides a warning if any of the settings you choose are illegal ...

Page 399: ...ober 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 3 shows page 3 of the ALT2GXB MegaWizard Plug In Manager in Basic mode Figure 4 3 MegaWizard Plug In Manager ALT2GXB General ...

Page 400: ... Basic Double Width mode Reverse serial loopback This is a loopback after the receiver s CDR block to the transmitter buffer The RX path in the PCS is active but the TX side is not Reverse serial loopback pre CDR This is the loopback before the receiver s CDR block to the transmitter buffer The RX path in the PCS is active but the TX side is not PRBS Serial loopback This is another serial loopback...

Page 401: ...one of following Enter a data rate and select an input clock frequency through a pull down menu with the data rate selection Enter your input clock frequency through a pull down menu with the data rate selection or enter your input clock frequency and select from the available data rates for a clock frequency What is the data rate Determines the TX and RX PLL VCO frequency What is the input clock ...

Page 402: ...evice Handbook Create tx_digitalreset port Transmitter digital reset port Resets the PCS portion of the transmitter Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Table 4 1 MegaWizard Plug In Manager Opt...

Page 403: ...er 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 4 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for Basic mode Figure 4 4 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 404: ...LL bandwidth selection of low medium and high The recommendations will be determined by characterization Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automatic re...

Page 405: ...e Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver A...

Page 406: ...mitter Phase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Clocking section in...

Page 407: ...2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 5 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for Basic mode Figure 4 5 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 408: ...book Force signal detection This option disables the signal detect circuit This removes the signal detect criterion for the receiver CRU lock to reference and lock to data switchover This option is available only in PIPE mode Receiver Buffer Section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the signal detect and signal l...

Page 409: ...ransceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create active low cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapte...

Page 410: ... Corporation Stratix II GX Device Handbook Volume 2 October 2007 Basic Mode Figure 4 6 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for Basic mode Figure 4 6 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 411: ...ndbook Use external Transmitter termination This option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This...

Page 412: ...r ALT2GXB Reconfig Pre emphasis first post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using first post tap Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap Table 4 4 MegaWizard Plug In Manager Options Page 6 for Basic Mode Part 2 of 2 ALT2GXB Setting Description Refe...

Page 413: ...econfiguration among modes that have different PLD interface signals Channel internals Enables MIF based reconfiguration among modes that have different data paths within the channel but have the same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX Dynam...

Page 414: ...nfig Alt PLL Table 4 8 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 6 MegaWizard Plug In Manager Options Page 8 for Basic Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the two PLLs in its transcei...

Page 415: ...n User Guide Figure 4 9 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for Basic mode This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page Page 7 Figure 4 9 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 416: ... current configuration Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver PLL Stratix II GX Dynamic Reconfigur...

Page 417: ...ALT2GXB Megafunction User Guide Figure 4 10 shows page 10 of the ALT2GXB MegaWizard Plug In Manager for Basic mode This page appears only if the Channel Internals or the Channel Interface option is selected in the Reconfig page Page 7 Figure 4 10 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 418: ...ansmitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically reverse the bit order at ...

Page 419: ...7 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 11 shows page 11 of the MegaWizard Plug In Manager for the Basic protocol mode set up Figure 4 11 MegaWizard Plug In Manager ALT2GXB Basic 1 ...

Page 420: ...Byte Ordering Block section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the byte ordering pad pattern Enter the pad pattern that the byte ordering block inserts until the byte ordering pattern can be placed in the LSByte position Byte Ordering Block section in the Stratix II GX Transceiver Architecture Overview chapter in ...

Page 421: ...he data at the receiver PLD interface at a byte level to support MSBit to LSBit transmission protocols The default transmission order is LSBit to MSBit Flip Transmitter input data bits This option reverses the bit order of the data bits at the input of the transmitter at a byte level to support MSBit to LSBit transmission protocols The default transmission order is LSBit to MSBit Enable Transmitte...

Page 422: ...ration Stratix II GX Device Handbook Volume 2 October 2007 Basic Mode Figure 4 12 shows page 12 of the MegaWizard Plug In Manager for the Basic protocol mode set up Figure 4 12 MegaWizard Plug In Manager ALT2GXB Basic 2 ...

Page 423: ... the built in synchronization state machine This option sets the word aligner to use the built in synchronization state machine The behavior is similar to the PIPE synchronization state machine with adjustable synchronization thresholds Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Number of bad data words befor...

Page 424: ...X Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Enable word aligner output reverse bit ordering In manual bit slip mode this option creates an input port rx_revbitorderwa to dynamically reverse the bit order at the output of the receiver word aligner In other Basic modes this option statically configures the receiver to always reverse the bit order of t...

Page 425: ...ix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_disperr port to indicate 8B 10B decoder has detected a disparity code Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port 8B 10B Decoder section in the Stratix II GX Transceiver Architecture O...

Page 426: ... Basic protocol mode set up The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for the third party EDA synthesis tool to estimate timing and resource utilization for the ALT2GXB instance Figure 4 13 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 427: ...ions click Finish to generate the files Figure 4 14 MegaWizard Plug In Manager ALT2GXB Summary Physical Interface for PCI Express PIPE Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the PIPE mode The MegaWizard Plug In Manager provides a warning if any of the settings you choose are illegal 1 The word aligner a...

Page 428: ...atix II GX Device Handbook Volume 2 October 2007 Physical Interface for PCI Express PIPE Mode Figure 4 15 shows page 3 of the ALT2GXB MegaWizard Plug In Manager for PIPE mode Figure 4 15 MegaWizard Plug In Manager ALT2GXB General ...

Page 429: ...r your design If you select this option all PIPE specific ports are used What is the operation mode Only the receiver and transmitter full duplex mode is allowed in the PIPE mode Receiver only and transmitter only modes are not allowed What is the number of channels This determines how many duplicate channels this ALT2GXB instance contains In a 4 subprotocol the number of channels increments by 4 ...

Page 430: ...of the Stratix II GX Device Handbook Create rx_analogreset port for the analog portion of the receiver Receiver analog reset port Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Createtx_digitalreset port for the digital portion of the transmitter Transmitter digital reset port Resets the PCS porti...

Page 431: ...1 of 4 ALT2GXB Setting Description Reference Train Receiver PLL clock from PLL inclk If you turn this option on your design uses the input reference clock to the transmitter PLL to train the receiver PLL This reduces the need to supply a separate receiver PLL reference clock If CMU PLL reconfiguration is enabled this option is automatically enabled by the Megawizard Plug In Manager Clock Recovery ...

Page 432: ... for information about this port Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create pll_locked port to indicate PLL is in lock with the reference input clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information abo...

Page 433: ...chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create debug_rx_phase_comp_fi fo_error output port This optional output port indicates Receiver Phase Compensation FIFO overflow underrun condition Note that no PPM difference...

Page 434: ...tix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create tx_coreclk port to connect to the write clock of the TX phase compensation FIFO This optional input port allows you to clock the write side of the Transmitter Phase Compensation FIFO with a non transceiver PLD clock Transmitter Phase Compensation FIFO section in the Stratix II GX Transceiver...

Page 435: ...shows page 5 of the ALT2GXB MegaWizard Plug In Manager for PIPE mode Figure 4 17 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk Note 1 Note to Figure 4 17 1 If the equalizer DC gain is controlled by the ALT2GXB_RECONFIG controller the rx_eqdcgain input to the ALT2GXB_RECONFIG controller should be tied to 01 to be PCI E compliant ...

Page 436: ...tratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Force signal detection This option disables the signal detect circuit This removes the signal detect criterion for the receiver CRU lock to reference and lock to data switchover Receiver Buffer Section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II G...

Page 437: ...ransceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create active low cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapte...

Page 438: ...tix II GX Device Handbook Volume 2 October 2007 Physical Interface for PCI Express PIPE Mode Figure 4 18 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for PIPE mode Figure 4 18 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 439: ...available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects the transmitter termination value This opti...

Page 440: ...tting of VOD This option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 14 MegaWizard Plug...

Page 441: ...mically enables adaptive equalization for the selected receiver channel Channel Interface Enables MIF based reconfiguration among modes that have different PLD interface signals Channel Internals Enables MIF based reconfiguration among modes that have different data paths within the channel but the same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel...

Page 442: ...In Manager ALT2GXB Reconfig Alt PLL Table 4 16 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 16 MegaWizard Plug In Manager Options Page 8 for PIPE Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the ...

Page 443: ...Guide Figure 4 21 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for PCI Express PIPE mode This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page Page 7 Figure 4 21 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 444: ...ck source for the current configuration Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver PLL Stratix II GX D...

Page 445: ...XB Megafunction User Guide Figure 4 22 shows page 10 of the MegaWizard Plug In Manager for the PIPE protocol selection This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page Page 7 Figure 4 22 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 446: ...ow should the transmitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically reverse t...

Page 447: ...X ALT2GXB Megafunction User Guide Figure 4 23 shows page 11 of the MegaWizard Plug In Manager for the PIPE protocol selection If the Enforce default settings for this protocol option is selected this page does not appear in the MegaWizard Figure 4 23 MegaWizard Plug In Manager ALT2GXB PCI ...

Page 448: ...cation in the PLD logic array PCI Express PIPE Mode section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Createrx_syncstatusoutput port for pattern detector and word aligner Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Word Alig...

Page 449: ...ix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port PIPE Mode section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create pipe8b 10binvpolarity to enable polarity inversion in PIPE Refer to the Stratix II GX Transceiver Architecture Overview chapter in ...

Page 450: ...ransceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_invpolarity to enable word aligner polarity inversion This optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner This feature must not be enabled when pipe8b 10binvpolarity is enabled Word Aligner section in the Stratix II GX Transceiver A...

Page 451: ... In Manager for the PIPE protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for the third party EDA synthesis tool to estimate timing and resource utilization for the ALT2GXB instance Figure 4 24 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 452: ...ns click Finish to generate the files Figure 4 25 MegaWizard Plug In Manager ALT2GXB Summary XAUI Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the XAUI mode The MegaWizard Plug In Manager provides a warning if any of the settings you choose are illegal 1 The word aligner and rate matcher operations and patter...

Page 453: ... describes the available options on page 3 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 20 MegaWizard Plug In Manager Options Page 3 for XAUI Mode Part 1 of 3 ALT2GXB Setting Description Reference Which protocol will you be using Selects the specific protocol or modes under which the transceiver operates For the XAUI or HiGig you must select the XAUI pro...

Page 454: ...hapter in volume 2 of the Stratix II GX Device Handbook What would you like to base the setting on This option is not available What is the data rate 1 Enter a data rate from 3 125 Gbps to 3 75 Gbps What is the input clock frequency Determines the input reference clock frequency for the transceiver The Quartus II software automatically selects the input reference clock frequency based on the enter...

Page 455: ...the PCS portion of the transmitter Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Note to Table 4 20 1 A data rate higher than 3 125 Gbps requires a 3 speed grade device The higher speed also requires a ...

Page 456: ...ceiver PLL and VCO Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automatic receiver CRU switchover between lock to data and lock to reference There are additional ...

Page 457: ...tix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Archite...

Page 458: ...hase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Clocking section in the Str...

Page 459: ...007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 28 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for XAUI mode Figure 4 28 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 460: ... the Stratix II GX Device Handbook What is the Receiver Common Mode Voltage RX VCM The receiver common mode voltage is set to 0 85 V Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Force signal detection This option is available only in PIPE mode Receiver Buffer Section in the Stratix II GX Transceiver Architec...

Page 461: ...alibration block Only one instance of ALT2GXB is required to instantiate the calibration block Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Dev...

Page 462: ... Corporation Stratix II GX Device Handbook Volume 2 October 2007 XAUI Mode Figure 4 29 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for XAUI mode Figure 4 29 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 463: ...ermination This option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects the transmitter t...

Page 464: ...option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 23 MegaWizard Plug In Manager Option...

Page 465: ...izer control Dynamically enables adaptive equalization for the selected receiver channel Channel Internals Enables MIF based reconfiguration to a XAUI mode with different internal parameters Note that the Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock options are not available in XAUI mode Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Strati...

Page 466: ...a Corporation Stratix II GX Device Handbook Volume 2 October 2007 XAUI Mode Figure 4 31 shows page 8 of the ALT2GXB MegaWizard Plug In Manager for XAUI mode Figure 4 31 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 467: ... the default mode Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis Altera recommends controlling all four channels simultaneously A digital reset must be asserted for the transceiver Loopback Modes section in the Stratix II ...

Page 468: ...tober 2007 XAUI Mode Figure 4 32 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for XAUI mode If the Enforce default settings for this protocol option is selected this page does not appear in the MegaWizard Figure 4 32 MegaWizard Plug In Manager ALT2GXB XAUI ...

Page 469: ...iver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_ctrldetect port to indicate 8B 10B decoder has detected a control code Refer to the Stratix II GX Transceiver Architecture Overview chapter i...

Page 470: ...Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create tx_invpolarity to allow Transmitter polarity inversion This optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter PCS PMA interface 8B 10B encoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device ...

Page 471: ...nager for the XAUI protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for the third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance Figure 4 33 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 472: ...ns click Finish to generate the files Figure 4 34 MegaWizard Plug In Manager ALT2GXB Summary GIGE Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the GIGE mode The MegaWizard Plug In Manager provides a warning if any of the settings you choose are illegal 1 The word aligner and rate matcher operations and patter...

Page 473: ...27 describes the available options on page 3 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 27 MegaWizard Plug In Manager Options Page 3 for GIGE Mode Part 1 of 3 ALT2GXB Setting Description Reference Which protocol will you be using Selects the specific protocol or modes under which the transceiver operates For the GIGE mode you must select the GIGE proto...

Page 474: ...tions in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What would you like to base the setting on This option is not used because the data rate is fixed at 1 25 Gbps for GIGE mode What is the data rate This option is not used because the data rate is fixed at 1 25 Gbps for GIGE mode What is the input clock frequency Determines the inpu...

Page 475: ...he Stratix II GX Device Handbook Createtx_digitalreset port for the digital portion of the receiver Transmitter digital reset port Resets the PCS portion of the transmitter Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX...

Page 476: ... Corporation Stratix II GX Device Handbook Volume 2 October 2007 GIGE Mode Figure 4 36 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode Figure 4 36 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 477: ...bandwidth mode In GIGE mode only medium bandwidth is supported for the receiver PLL and VCO Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automatic receiver CRU sw...

Page 478: ...ver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview cha...

Page 479: ...urpose only Transmitter Phase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Cl...

Page 480: ...poration Stratix II GX Device Handbook Volume 2 October 2007 GIGE Mode Figure 4 37 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode Figure 4 37 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 481: ...ode voltage is set to 0 85 V Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Forced signal detection This option disables the signal detect circuit This removes the signal detect criterion for the receiver CRU lock to reference and lock to data switchover Receiver Buffer Section in the Stratix II GX Transceiver...

Page 482: ...nly one instance of ALT2GXB is required to instantiate the calibration block Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for i...

Page 483: ...er 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 38 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode Figure 4 38 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 484: ...tion is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects the transmitter termination value T...

Page 485: ...tting of VOD This option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 30 MegaWizard Plug...

Page 486: ...n among modes that have different PLD interface signals Channel Internals Enables MIF based reconfiguration among modes that have different data paths within the channel but same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX Dynamic Reconfiguration cha...

Page 487: ...nfig Alt PLL Table 4 32 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 32 MegaWizard Plug In Manager Options Page 8 for GIGE Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the two PLLs in its transce...

Page 488: ... 4 41 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected on the Reconfig page Page 7 Figure 4 41 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 489: ...urrent configuration Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver ...

Page 490: ...007 GIGE Mode Figure 4 42 shows page 10 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode This page appears only when the Channel Internals and Channel Interface options are selected in the Reconfig page Page 7 Figure 4 42 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 491: ...How should the transmitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically reverse ...

Page 492: ... Corporation Stratix II GX Device Handbook Volume 2 October 2007 GIGE Mode Figure 4 43 shows page 11 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode Figure 4 43 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 493: ...e default mode Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis Altera recommends controlling all four channels simultaneously A digital reset must be asserted for the transceiver Loopback Modes section in the Stratix II GX ...

Page 494: ...tober 2007 GIGE Mode Figure 4 44 shows page 12 of the ALT2GXB MegaWizard Plug In Manager for GIGE mode If the Enforce default settings for this protocol option is selected this page does not appear in the MegaWizard Figure 4 44 MegaWizard Plug In Manager ALT2GXB GIGE ...

Page 495: ...eiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_ctrldetect port to indicate 8B 10B decoder has detected a control code Refer to the Stratix II GX Transceiver Architecture Overview chapter ...

Page 496: ...Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create tx_invpolarity to allow Transmitter polarity inversion This optional port allows you to dynamically reverse the polarity of the data to be transmitted at the transmitter PCS PMA interface 8B 10B encoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device ...

Page 497: ... Manager for the GIGE protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance Figure 4 45 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 498: ...t optional files on this page After you make your selections click Finish to generate the files Figure 4 46 MegaWizard Plug In Manager ALT2GXB Summary SONET SDH Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the SONET SDH mode The MegaWizard Plug In Manager provides a warning if any of the settings you choose a...

Page 499: ...r 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 47 shows page 3 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode Figure 4 47 MegaWizard Plug In Manager ALT2GXB General ...

Page 500: ...ports are used and the defaulted alignment pattern is locked at 16 hF628 What is the operation mode The transmitter only receiver only and receiver and transmitter full duplex modes are allowed in the SONET SDH protocol What is the number of channels This selects how many duplicate channels this ALT2GXB instance contains In SONET SDH mode the number of channels increments by 1 What is the deserial...

Page 501: ...the receiver Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_analogreset port for the analog portion of the receiver Receiver analog reset port Reset Control and Power Down section in the Strati...

Page 502: ...poration Stratix II GX Device Handbook Volume 2 October 2007 SONET SDH Mode Figure 4 48 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode Figure 4 48 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 503: ...ver PLL bandwidth mode This option is not available in SONET SDH mode because the receiver PLL bandwidth is fixed at medium Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affec...

Page 504: ...iver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview ch...

Page 505: ...pose only Transmitter Phase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Cloc...

Page 506: ...tion Stratix II GX Device Handbook Volume 2 October 2007 SONET SDH Mode Figure 4 49 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode Figure 4 49 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 507: ...on mode voltage is set to 0 85 V Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Force signal detection This option disables the signal detect circuit This removes the signal detect criterion for the receiver CRU lock to reference and lock to data switchover Receiver Buffer Section in the Stratix II GX Transcei...

Page 508: ...ne instance of ALT2GXB is required to instantiate the calibration block Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create active low cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook...

Page 509: ... 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 50 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode Figure 4 50 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 510: ...his option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects the transmitter termination v...

Page 511: ...etting of VOD This option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 40 MegaWizard Plu...

Page 512: ...uration among modes that have different PLD interface signals Channel Internals Enables MIF based reconfiguration among modes that have different data paths within the channel but same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX Dynamic Reconfigurati...

Page 513: ...ser Guide Figure 4 52 shows page 8 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page Page 7 Figure 4 52 MegaWizard Plug In Manager ALT2GXB Reconfig Alt PLL ...

Page 514: ... and Transmitter PLL Reconfiguration options are selected in the Reconfig page Page 7 Figure 4 53 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 Table 4 42 MegaWizard Plug In Manager Options Page 8 for SONET SDH Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the two PLLs in its ...

Page 515: ...clock source for the current configuration Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver PLL Stratix II G...

Page 516: ...SONET SDH Mode Figure 4 54 shows page 10 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page Page 7 Figure 4 54 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 517: ...ok How should the transmitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically rever...

Page 518: ...poration Stratix II GX Device Handbook Volume 2 October 2007 SONET SDH Mode Figure 4 55 shows page 11 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode Figure 4 55 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 519: ...is is the default mode Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis Altera recommends controlling all four channels simultaneously A digital reset must be asserted for the transceiver Loopback Modes section in the Strati...

Page 520: ... 2007 SONET SDH Mode Figure 4 56 shows page 12 of the ALT2GXB MegaWizard Plug In Manager for SONET SDH mode If the Enforce default settings for this protocol option is selected this page does not appear in the MegaWizard Figure 4 56 MegaWizard Plug In Manager ALT2GXB SONET ...

Page 521: ...re Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the word alignment pattern Enter the word alignment pattern here By default the pattern that appears in the MegaWizard Plug In Manager is 0001010001101111 16 h146F SONET SDH Mode OC 12 OC 48 and OC 96 section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Fl...

Page 522: ...fer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_invpolarity to enable word aligner polarity inversion This optional port allows you to dynamically reverse th...

Page 523: ...ix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Flip Transmitter input data bits This option reverse the bit order of the transmitter input data tx_datain at a byte level to support MSB to LSB transmission protocols such as SONET SDH SONET SDH Mode OC 12 OC 48 and OC 96 section in the Stratix II GX Transceiver Architecture Overview chapter in vol...

Page 524: ...ONET SDH protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance Figure 4 57 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 525: ... select optional files on this page After you make your selections click Finish to generate the files Figure 4 58 MegaWizard Plug In Manager ALT2GXB Summary OIF CEI PHY Interface Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the OIF CEI PHY Interface mode The MegaWizard Plug In Manager provides a warning if an...

Page 526: ... 3 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 47 MegaWizard Plug In Manager Options Page 3 for OIF CEI PHY Interface Mode Part 1 of 3 ALT2GXB Setting Description Reference Which protocol will you be using Selects the specific protocol or modes that the transceiver operates under For the OIF CEI PHY Interface mode you must select the OIF CEI PHY Interfa...

Page 527: ...ption is fixed to Data rate in OIF CEI PHY Interface mode What is the data rate This field allows you to enter the data rate In OIF CEI PHY mode you can enter a data rate between 3125 Gbps and 6375 Gbps OIF CEI PHY Interface Mode section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the input clock frequency This field allow...

Page 528: ...vice Handbook Createtx_digitalreset port for the digital portion of the transmitter Transmitter digital reset port Resets the PCS portion of the transmitter Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook...

Page 529: ...Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 60 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for OIF CEI PHY Interface mode Figure 4 60 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 530: ... bandwidth mode In OIF CEI PHY Interface mode only medium bandwidth is supported for the receiver PLL and VCO Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automat...

Page 531: ...X Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Ov...

Page 532: ...mitter Phase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Clocking section in...

Page 533: ...tix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 61 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for OIF CEI PHY Interface mode Figure 4 61 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 534: ...ode voltage is set to 0 85 V Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Force signal detection This option disables the signal detect circuit This removes the signal detect criterion for the receiver CRU lock to reference and lock to data switchover Receiver Buffer section in the Stratix II GX Transceiver ...

Page 535: ...on block Only one instance of ALT2GXB is required to instantiate the calibration block Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Hand...

Page 536: ...atix II GX Device Handbook Volume 2 October 2007 OIF CEI PHY Interface Mode Figure 4 62 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for OIF CEI PHY Interface mode Figure 4 62 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 537: ...al Transmitter termination This option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects t...

Page 538: ...VOD This option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 50 MegaWizard Plug In Manag...

Page 539: ...es MIF based reconfiguration among modes that have different PLD interface signals Channel Internals Enables MIF based reconfiguration among modes that have different data paths within the channel but same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX ...

Page 540: ...XB Reconfig Alt PLL Table 4 52 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 52 MegaWizard Plug In Manager Options Page 8 for OIF CEI PHY Interface Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the...

Page 541: ...Guide Figure 4 65 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for OIF CEI PHY Interface mode This page appears only if the Channel Internals and Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page Page 7 Figure 4 65 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 542: ...k source for the current configuration Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver PLL Stratix II GX Dy...

Page 543: ...function User Guide Figure 4 66 shows page 10 of the MegaWizard Plug In Manager for the OIF CEI PHY Interface protocol selection This page appears only when the Channel Internals or Channel Interface option is selected in the Reconfig page Page 7 Figure 4 66 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 544: ...ow should the transmitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically reverse t...

Page 545: ...ix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 67 shows page 11 of the MegaWizard Plug In Manager for the OIF CEI PHY Interface protocol selection Figure 4 67 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 546: ...s the default mode Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis Altera recommends controlling all four channels simultaneously A digital reset must be asserted for the transceiver Loopback Modes section in the Stratix II...

Page 547: ...s for this protocol option is selected this page does not appear in the MegaWizard The Use central clock divider to improve transmitter jitter option allows you to set up bundled clocking for channels within the same transceiver block to improve transmitter jitter performance This option is not available if the Channel Interface or Channel Internals options with alternate PLL or CMU PLL reconfigur...

Page 548: ...IF CEI PHY Interface protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance Figure 4 69 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 549: ...protocol set up You can select optional files on this page After you make your selections click Finish to generate the files Figure 4 70 MegaWizard Plug In Manager ALT2GXB Summary CPRI Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the CPRI mode The MegaWizard Plug In Manager provides a warning if any of the se...

Page 550: ...le options on page 3 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 56 MegaWizard Plug In Manager Options Page 3 for CPRI Mode Part 1 of 3 ALT2GXB Setting Description Reference Which protocol will you be using Selects the specific protocol or modes under which the transceiver operates For the CPRI mode you must select the CPRI protocol Which subprotocol wi...

Page 551: ... interface width In CPRI mode 8 bits are allowed Byte Serializer and Byte Deserializer sections in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What would you like to base the setting on This option is forced to Data rate What is the data rate Three CPRI data rates are supported 614 Mbps 1228 Mbps 2456 Mbps What is the input clock fre...

Page 552: ...vice Handbook Createtx_digitalreset port for the digital portion of the transmitter Transmitter digital reset port Resets the PCS portion of the transmitter Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook...

Page 553: ...ber 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 72 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode Figure 4 72 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 554: ... CPRI mode only medium bandwidth is supported for the receiver PLL and VCO Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automatic receiver CRU switchover between ...

Page 555: ...atix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Archit...

Page 556: ...mitter Phase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Clocking section in...

Page 557: ...2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 73 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode Figure 4 73 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 558: ...t to 0 85 V Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Forced signal detection This option disables the signal detect circuit This removes the signal detect criterion for the receiver CRU lock to reference and lock to data switchover Receiver Buffer Section in the Stratix II GX Transceiver Architecture Ove...

Page 559: ...calibration block Only one instance of ALT2GXB is required to instantiate the calibration block Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX De...

Page 560: ...a Corporation Stratix II GX Device Handbook Volume 2 October 2007 CPRI Mode Figure 4 74 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode Figure 4 74 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 561: ...termination This option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects the transmitter ...

Page 562: ... option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 59 MegaWizard Plug In Manager Optio...

Page 563: ...ased reconfiguration among modes that have different PLD interface signals Channel Internals Enables MIF based reconfiguration among modes that have different data paths within the channel but same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX Dynamic ...

Page 564: ... 4 61 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 61 MegaWizard Plug In Manager Options Page 8 for CPRI Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the two PLLs in its transceiver block The inf...

Page 565: ...n User Guide Figure 4 77 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected on the Reconfig page Page 7 Figure 4 77 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 566: ...on Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver PLL Stratix II GX ...

Page 567: ... ALT2GXB Megafunction User Guide Figure 4 78 shows page 10 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page Page 7 Figure 4 78 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 568: ...nsmitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically reverse the bit order at t...

Page 569: ...ber 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 79 shows page 11 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode Figure 4 79 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 570: ...e Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis Altera recommends controlling all four channels simultaneously A digital reset must be asserted for the transceiver Loopback Modes section in the Stratix II GX Transceiver A...

Page 571: ...II GX ALT2GXB Megafunction User Guide Figure 4 80 shows page 12 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode If the Enforce default settings for this protocol option is selected this page does not appear in the MegaWizard Figure 4 80 MegaWizard Plug In Manager ALT2GXB CPRI 1 ...

Page 572: ...ce disparity and use tx_dispval to code up the incoming word using positive or negative disparity This option allows you to force positive or negative disparity on transmitted data in 8B 10B configurations 8B 10 Encoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Enable rate match FIFO This option is not available in CPRI ...

Page 573: ...d aligner polarity inversion This optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create tx_invpolarity to allow Transmitter polarity inversion This optional port allows you to dynamically reverse the...

Page 574: ...ra Corporation Stratix II GX Device Handbook Volume 2 October 2007 CPRI Mode Figure 4 81 shows page 13 of the ALT2GXB MegaWizard Plug In Manager for CPRI mode Figure 4 81 MegaWizard Plug In Manager ALT2GXB CPRI 2 ...

Page 575: ...tratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Number of bad data words before loss of synch state Use this option with the built in state machine to transition from a synchronized state to an unsynchronized state Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handb...

Page 576: ...checking with a run length of This option activates the run length violation circuit You can program the run length at which the circuit triggers the rx_rlv signal Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Enable word aligner output reverse bit ordering This option statically configures the receiver to rever...

Page 577: ...t to indicate 8B 10B decoder has detected an error code Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port 8B 10B Decoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_disperr port to indicate 8B 10B decoder has detec...

Page 578: ...PRI protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance Figure 4 82 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 579: ... set up You can select optional files on this page After you make your selections click Finish to generate the files Figure 4 83 MegaWizard Plug In Manager ALT2GXB Summary SDI Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for the SDI mode The MegaWizard Plug In Manager provides a warning if any of the settings you...

Page 580: ...era Corporation Stratix II GX Device Handbook Volume 2 October 2007 SDI Mode Figure 4 84 shows page 3 of the ALT2GXB MegaWizard Plug In Manager for SDI mode Figure 4 84 MegaWizard Plug In Manager ALT2GXB General ...

Page 581: ...duplicate channels this ALT2GXB instance contains What is the deserializer block width SDI mode only operates in a single width mode Double width mode is not allowed What is the channel width This option determines the transceiver to PLD interface width In SDI mode 10 bit and 20 bit channel widths are allowed In 10 bit configuration the byte serializer is not used In 20 bit configuration the byte ...

Page 582: ...k Create rx_analogreset port for the analog portion of the receiver Receiver analog reset port Reset Control and Power Down section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Createtx_digitalreset port for the digital portion of the receiver Transmitter digital reset port Resets the PCS portion of the transmitter Altera recommend...

Page 583: ...ber 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 85 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for SDI mode Figure 4 85 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 584: ... Three available bandwidth options are high medium and low The default receiver PLL bandwidth is medium Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automatic rec...

Page 585: ...atix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Archit...

Page 586: ...ct to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Clocking section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create tx_coreclk port to connect to the write clock of the TX phase com...

Page 587: ...2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 86 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for SDI mode Figure 4 86 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 588: ...f the Stratix II GX Device Handbook What is the Receiver Common Mode Voltage RX VCM The receiver common mode voltage is set to 0 85 V Receiver Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Force signal detection This option if force selected in SDI mode Receiver Buffer Section in the Stratix II GX Transceiver Architec...

Page 589: ...calibration block Only one instance of ALT2GXB is required to instantiate the calibration block Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX De...

Page 590: ...ra Corporation Stratix II GX Device Handbook Volume 2 October 2007 SDI Mode Figure 4 87 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for SDI mode Figure 4 87 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 591: ...ermination This option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option selects the transmitter t...

Page 592: ...option sets the amount of pre emphasis on the transmitter buffer using first post tap The amount of pre emphasis is to be determined by characterization Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap The amount of pre emphasis is to be determined by characterization Table 4 70 MegaWizard Plug In Manager Option...

Page 593: ...sed reconfiguration among modes that have different PLD interface signals Channel Internals Enables MIF based reconfiguration among modes that have different data paths within the channel but same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX Dynamic R...

Page 594: ... 4 72 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 72 MegaWizard Plug In Manager Options Page 8 for SDI Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of the two PLLs in its transceiver block The info...

Page 595: ...ion User Guide Figure 4 90 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for SDI mode This page appears only if the Channel Internals and Enable Channel and Transmitter PLL Reconfiguration options are selected on the Reconfig page Page 7 Figure 4 90 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 596: ...n Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver PLL option you can select the clock source for the alternate Transmitter PLL and the Receiver PLL Stratix II GX D...

Page 597: ... ALT2GXB Megafunction User Guide Figure 4 91 shows page 10 of the ALT2GXB MegaWizard Plug In Manager for SDI mode This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page Page 7 Figure 4 91 MegaWizard Plug In Manager ALT2GXB Reconfig 2 ...

Page 598: ...smitters be clocked Two options are available Share a single transmitter core clock between transmitters Use the respective channel transmitter core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbitorderwa input port to use receiver enable bit reversal This optional input port allows you to dynamically reverse the bit order at th...

Page 599: ...ber 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 92 shows page 11 of the ALT2GXB MegaWizard Plug In Manager for SDI mode Figure 4 92 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 600: ... Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis Altera recommends controlling all four channels simultaneously A digital reset must be asserted for the transceiver Loopback Modes section in the Stratix II GX Transceiver Ar...

Page 601: ... II GX ALT2GXB Megafunction User Guide Figure 4 93 shows page 12 of the ALT2GXB MegaWizard Plug In Manager for SDI mode If the Enforce default settings for this protocol option is selected this page does not appear in the MegaWizard Figure 4 93 MegaWizard Plug In Manager ALT2GXB SDI 1 ...

Page 602: ... disparity and use tx_dispval to code up the incoming word using positive or negative disparity This option allows you to force positive or negative disparity on transmitted data in 8B 10B configurations 8B 10 Encoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Enable rate match FIFO This option is not available in SDI mod...

Page 603: ...d aligner polarity inversion This optional port allows you to dynamically reverse the polarity of the received data at the input of the word aligner Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create tx_invpolarity to allow Transmitter polarity inversion This optional port allows you to dynamically reverse the...

Page 604: ...era Corporation Stratix II GX Device Handbook Volume 2 October 2007 SDI Mode Figure 4 94 shows page 13 of the ALT2GXB MegaWizard Plug In Manager for SDI mode Figure 4 94 MegaWizard Plug In Manager ALT2GXB SDI 2 ...

Page 605: ...X Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Number of bad data words before loss of synch state Use this option with the built in synchronization state machine to transition from a synchronized state to an unsynchronized state Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device ...

Page 606: ...checking with a run length of This option activates the run length violation circuit You can program the run length at which the circuit triggers the rx_rlv signal Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Enable word aligner output reverse bit ordering This option statically configures the receiver to rever...

Page 607: ...rt to indicate 8B 10B decoder has detected an error code Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port 8B 10B Decoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_disperr port to indicate 8B 10B decoder has dete...

Page 608: ...DI protocol selection The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance Figure 4 95 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 609: ...ou can select optional files on this page After you make your selections click Finish to generate the files Figure 4 96 MegaWizard Plug In Manager ALT2GXB Summary Serial RapidIO Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug In Manager for Serial RapidIO mode The MegaWizard Plug In Manager provides a warning if any of the set...

Page 610: ... your ALT2GXB custom megafunction variation Table 4 78 MegaWizard Plug In Manager Options Page 3 for Serial RapidIO Mode Part 1 of 2 ALT2GXB Setting Description Reference Which protocol will you be using Determines the specific protocol or modes under which the transceiver operates For Serial RapidIO mode you must select the Serial RapidIO protocol Which subprotocol will you be using This option i...

Page 611: ...clock frequency you want as a reference clock for the transceiver What is the data rate division factor This option is not available in Serial RapidIO mode Create rx_digitalreset port Receiver digital reset port Resets the PCS portion of the receiver Altera recommends using this port along with logic to implement the recommended reset sequence Reset Control and Power Down section in the Stratix II...

Page 612: ...ion Stratix II GX Device Handbook Volume 2 October 2007 Serial RapidIO Mode Figure 4 98 shows page 4 of the ALT2GXB MegaWizard Plug In Manager for Serial RapidIO mode Figure 4 98 MegaWizard Plug In Manager ALT2GXB PLL Ports ...

Page 613: ...width mode The Quartus II software automatically selects the medium bandwidth setting in Serial RapidIO mode Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the acceptable PPM threshold between the Receiver PLL VCO and the CRU clock This option determines the PPM difference that affects the automati...

Page 614: ...ransceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_pll_locked port to indicate RX PLL is in lock with the reference clock Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Clock Recovery Unit section in the Stratix II GX Transceiver Architecture Overv...

Page 615: ...se only Transmitter Phase Compensation FIFO section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_coreclk port to connect to the read clock of the RX phase compensation FIFO This optional input port allows you to clock the read side of the Receiver Phase Compensation FIFO with a non transceiver PLD clock Transceiver Clocki...

Page 616: ...Stratix II GX Device Handbook Volume 2 October 2007 Serial RapidIO Mode Figure 4 99 shows page 5 of the ALT2GXB MegaWizard Plug In Manager for Serial RapidIO mode Figure 4 99 MegaWizard Plug In Manager ALT2GXB RX Analog Cal Blk ...

Page 617: ... Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Force signal detection This option is available only in PIPE mode Receiver Buffer Section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook What is the signal detect and signal loss threshold Use this option when the forced signal d...

Page 618: ...cture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create active low cal_blk_powerdown to power down the calibration block Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port Calibration Blocks section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of t...

Page 619: ...07 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide Figure 4 100 shows page 6 of the ALT2GXB MegaWizard Plug In Manager for Serial RapidIO mode Figure 4 100 MegaWizard Plug In Manager ALT2GXB TX Analog ...

Page 620: ...Use external Transmitter termination This option is available if you want to use an external termination resistor instead of the on chip termination OCT Checking this option turns off the transmitter OCT Transmitter Buffer section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Select the Transmitter termination resistance This option...

Page 621: ...izard Plug In Manager ALT2GXB Reconfig Pre emphasis first post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using first post tap Pre emphasis second post tap setting of VOD This option sets the amount of pre emphasis on the transmitter buffer using second post tap Table 4 81 MegaWizard Plug In Manager Options Page 6 for Serial RapidIO Mode Part 2 of 2 AL...

Page 622: ...uration among modes that have different PLD interface signals Channel internals Enables MIF based reconfiguration among modes that have different data paths within the channel but have the same PLD interface signals When this option is enabled two mutually exclusive options Enable Channel and Transmitter PLL Reconfiguration and Use alternate reference clock are available Stratix II GX Dynamic Reco...

Page 623: ...nager ALT2GXB Reconfig Alt PLL Table 4 83 describes the available options on page 8 of the MegaWizard Plug In Manager for your ALT2GXB custom megafunction variation Table 4 83 MegaWizard Plug In Manager Options Page 8 for Serial RapidIO Mode ALT2GXB Setting Description Reference Use alternate Transmitter PLL and Receiver PLL Selecting this option sets up the transmitter channel to listen to one of...

Page 624: ... 4 103 shows page 9 of the ALT2GXB MegaWizard Plug In Manager for Serial RapidIO mode This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page Page 7 Figure 4 103 MegaWizard Plug In Manager ALT2GXB Reconfig Clks 1 ...

Page 625: ...one input reference clock sources for the transmitter and or receiver PLL this option allows you to select the clock source for the current configuration Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook What is the selected input clock source for the alternate Transmitter PLL and Receiver PLL If you select the Use alternate Transmitter PLL and Receiver...

Page 626: ...cription Reference How should the receivers be clocked Three options are available Share a single transmitter core clock between receivers Use the respective channel transmitter core clock Use the respective channel receiver core clocks Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook How should the transmitters be clocked Two options are available Sha...

Page 627: ...on in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of theStratix II GXDevice Handbook Check a control box to use the corresponding control port You can select various control and status signals depending on what protocol s you intend to dynamically reconfigure the transceiver to Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handboo...

Page 628: ...on Stratix II GX Device Handbook Volume 2 October 2007 Serial RapidIO Mode Figure 4 105 shows page 11 of the ALT2GXB MegaWizard Plug In Manager for Serial RapidIO mode Figure 4 105 MegaWizard Plug In Manager ALT2GXB Loopback ...

Page 629: ...serial loopback No loopback this is the default mode Serial loopback if you select serial loopback the rx_seriallpbken port is available to control the serial loopback feature dynamically A 1 b1 enables serial loopback and a 1 b0 disables loopback on a channel by channel basis A digital reset must be asserted for the transceiver Loopback Modes section in the Stratix II GX Transceiver Architecture ...

Page 630: ...tratix II GX Device Handbook Volume 2 October 2007 Serial RapidIO Mode Figure 4 106 shows page 12 of the MegaWizard Plug In Manager for the Serial RapidIO protocol set up Figure 4 106 MegaWizard Plug In Manager ALT2GXB SR I O 1 ...

Page 631: ... This option is not available in Serial RapidIO mode Rate Matcher section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Flip Receiver output data bits This option is not available in Serial RapidIO mode Flip Transmitter input data bits This option is not available in Serial RapidIO mode Enable Transmitter bit reversal This option in...

Page 632: ...tratix II GX Device Handbook Volume 2 October 2007 Serial RapidIO Mode Figure 4 107 shows page 13 of the MegaWizard Plug In Manager for the Serial RapidIO protocol set up Figure 4 107 MegaWizard Plug In Manager ALT2GXB SR I O 2 ...

Page 633: ...ization state machine based Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Number of bad data words before loss of synch state The Quartus II software forces this field to 3 to comply with the Serial RapidIO specification Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volum...

Page 634: ...er of the data at the output of the word aligner Word Aligner section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_syncstatus output port for pattern detector and word aligner Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this po...

Page 635: ... to indicate 8B 10B decoder has detected a disparity code Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about this port 8B 10B Decoder section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook Create rx_revbyteorderwa to enable receiver symbol swap T...

Page 636: ...the Serial RapidIO protocol set up The Generate simulation model creates a behavioral model vo or vho of the transceiver instance for third party simulators The Generate Netlist option generates a netlist for the third party EDA synthesis tool to estimate timing and resource utilization for the ALT2GXB instance Figure 4 108 MegaWizard Plug In Manager ALT2GXB EDA ...

Page 637: ... You can select optional files on this page After you make your selections click Finish to generate the files Figure 4 109 MegaWizard Plug In Manager ALT2GXB Summary Referenced Documents This chapter references the following documents Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Stratix II GX Transceiver Architecture Overview chapter in volume 2 of...

Page 638: ...e 4 32 Updated Table 4 16 Updated Reference column in Table 4 2 Updated Figure 4 22 Formerly chapter 3 The chapter number changed due to the addition of the Stratix II GX Dynamic Reconfiguration chapter February 2007 v4 0 Added the Document Revision History section to this chapter This entire chapter was updated All the tables were updated and all new graphics were included June 2006 v3 2 Updated ...

Page 639: ...2 Stratix II GX ALT2GXB Megafunction User Guide December 2005 v2 0 Added XAUI GIGE and SONET sections October 2005 v1 0 Added chapter to the Stratix II GX Device Handbook Table 4 89 Document Revision History Part 2 of 2 Date and Document Version Changes Made Summary of Changes ...

Page 640: ...4 244 Altera Corporation Stratix II GX Device Handbook Volume 2 October 2007 Document Revision History ...

Page 641: ...Altera Corporation 4 245 October 2007 Stratix II GX Device Handbook Volume 2 Stratix II GX ALT2GXB Megafunction User Guide ...

Page 642: ...4 246 Altera Corporation Stratix II GX Device Handbook Volume 2 October 2007 Document Revision History ...

Page 643: ...s menu When working in the Block Editor schematic symbol click MegaWizard Plug In Manager in the Symbol dialog box Edit menu Insert Symbol Start the stand alone version of the MegaWizard Plug In Manager by typing the following command at the command prompt qmegawiz Dynamic Reconfiguration This section provides descriptions of the options available on the individual pages of the ALT2GXB_RECONFIG Me...

Page 644: ...ions click Next when you are done ALT2GXB_RECONFIG megafunction option under the I O folder Stratix II GX as the device family Your desired type of output file format Verilog VHDL or AHDL Your desired file name 1 For the design to compile successfully you must enable the dynamic reconfiguration controller in the alt2gxb instance Figure 5 2 MegaWizard Plug In Manager ALT2GXB_RECONFIG Page 2 ...

Page 645: ...ou would like to activate for example Analog controls Channel Reconfiguration change the local divider values of the transmitter or Channel and TX PLL reconfiguration Figure 5 3 MegaWizard Plug In Manager ALT2GXB_RECONFIG Reconfiguration Settings Table 5 1 describes the available options on page 3 of the MegaWizard Plug In Manager for your ALT2GXB_RECONFIG custom megafunction variation Select the ...

Page 646: ... this setting Altera recommends that if there are multiple controllers for multiple instances of alt2gxb then the setting is same as the number of channels set in the alt2gxb instance If a single controller controls multiple instances of alt2gxb the setting is rounded up to the multiple of the nearest transceiver for the number of transceivers needed to fit the channels selected for that instance ...

Page 647: ...ck divider Division factors of 1 2 and 4 are supported For example dynamic rate switching of the transmitter from 4 Gbps to 2 Gbps to 1 Gbps Channel and TX PLL select reconfig The following three features are available under this option TX PLL reconfiguration Allows dynamic reconfiguration of the TX PLL only Channel and TX PLL reconfiguration Allows dynamic reconfiguration of the transceiver chann...

Page 648: ...s only if Analog Controls is selected in the What are the features to be reconfigured by the reconfig controller setting on page 3 Figure 5 4 MegaWizard Plug In Manager ALT2GXB_RECONFIG Analog Controls Table 5 2 describes the available options on page 4 of the MegaWizard Plug In Manager for your ALT2GXB_RECONFIG custom megafunction variation Make your selections on page 4 and click Next ...

Page 649: ...ecause it is not applicable for a one channel instance If the number of channels controlled by the controller is more than one this setting is enabled The setting is checked if the design needs the same control signal written into all channels simultaneously If the design requires the control signal to write in and read out of individual channels then the setting is not checked Dynamic Reconfigura...

Page 650: ...atix II GX Device Handbook Read Control PMA read control signals are Voltage Output Differential VOD Pre emphasis control pre tap 4 bits per channel Pre emphasis control 1st post tap 4 bits per channel Pre emphasis control 2nd post tap 4 bits per channel Equalizer control 4 bits per channel Equalizer DC gain 2 bits per channel These are optional signals The signal widths are based on the setting y...

Page 651: ... only if Channel Reconfiguration is selected in the What are the features to be reconfigured by the reconfig controller setting on page 3 Figure 5 5 MegaWizard Plug In Manager ALT2GXB_RECONFIG Channel and TX PLL Reconfiguration Table 5 3 describes the available options on page 5 of the MegaWizard Plug In Manager for your ALT2GXB_RECONFIG custom megafunction variation Make your signal selection on ...

Page 652: ...om 0 to 37 Therefore the width of the reconfig_address_out is set to either 5 bits or 6 bits wide depending on the feature selected The dynamic reconfiguration controller automatically increments the address at the end of each write cycle Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Use reconfig_address_en When high this optional output status sign...

Page 653: ...e TX PLL selected by this signal Channel and CMU PLL Reconfiguration section in the Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Use logical_tx_pll_sel_en This is an optional control signal When this signal is enabled in the ALT2GXB_Reconfig Megawizard the value set on the logical_tx_pll_sel signal is valid only if the logical_tx_pll_sel_en is set ...

Page 654: ... Data rate division in TX is selected in the What are the features to be reconfigured by the reconfig controller setting on page 3 Figure 5 6 MegaWizard Plug In Manager ALT2GXB_RECONFIG Error Checks Data Rate Switch Table 5 4 describes the available options on page 6 of the MegaWizard Plug In Manager for your ALT2GXB_RECONFIG custom megafunction variation Make your selections on page 6 and click N...

Page 655: ... operation Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Enable self recovery When this option is selected the ALT2GXB_RECONFIG MegaWizard provides the error output port The dynamic reconfiguration controller quits an operation if it did not complete within the expected number of clock cycles After recovering from the illegal operation the dynamic r...

Page 656: ...page 7 of the MegaWizard Plug In Manager for your ALT2GXB_RECONFIG custom megafunction variation Make your selections on page 7 and click Next Table 5 5 MegaWizard Plug In Manager Options Page 7 ALT2GXB_RECONFIG Setting Description Generate a netlist for synthesis area and timing estimation Selecting this option generates a netlist file that third party synthesis tools can use to estimate the timi...

Page 657: ... In Manager for the Dynamic Reconfiguration protocol set up You can select optional files on this page After you make your selections click Finish to generate the files Figure 5 8 MegaWizard Plug In Manager ALT2GXB_RECONFIG Summary Referenced Document This chapter references the following document Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook ...

Page 658: ...hanged due to the addition of the Stratix II GX Dynamic Reconfiguration chapter February 2007 v1 2 Modified Introduction Removed one sentence Added the Document Revision History section to this chapter Changed alt2gxb_reconfig to ALT2GXB_RECONFIG throughout Per new style guide convention Added more information describing Figures 5 2 and 5 3 Updated Use reconfig_address_out section of Table 5 3 Upd...

Page 659: ...h Single width Single or double width Native protocol support Basic XAUI GIGE SONET SDH Basic XAUI GIGE SONET SDH OC 12 OC 48 OC 96 PIPE OIF CEI PHY Interface CPRI Serial RapidIO SDI CMU Transmitter PLL Single transmitter PLL for entire transceiver block Multiple transmitter PLLs REFCLK One reference clock per transceiver block Two reference clocks per transceiver block 8B 10B Polarity inversion v...

Page 660: ...nd GIGE modes Byte ordering v Loopback Serial v v All modes except PCI Express PIPE mode Parallel v v Only in Basic mode Reverse serial v v no longer dynamic PIPE reverse parallel v PIPE mode only Post 8B 10B v BIST PRBS 7 v Only in Basic double width mode PRBS 8 1 v PRBS 10 v v Only in Basic double width mode Low frequency 2 v High frequency 2 v Mixed frequency 2 v Incremental 2 v v Only in paral...

Page 661: ...ach 8 bit code The 10 bit codes have either a neutral disparity or a non neutral disparity With neutral disparity two neutral disparity 10 bit codes are associated with an 8 bit code With non neutral disparity 10 bit code a positive and a negative disparity code are associated with the 8 bit code The positive disparity 10 bit code is associated in the RD column The negative disparity 10 bit code i...

Page 662: ...ub block is 4 b0011 The current running disparity at the end of a sub block is negative if any of the following is true The sub block contains more zeros than ones The 6 bit sub block is 6 b111000 The 4 bit sub block is 4 b1100 If those conditions are not met the running disparity at the end of the sub block is the same as at the beginning of the sub block Supported Codes The 8B 10B scheme defines...

Page 663: ...6 2 Supported K Codes Part 2 of 2 K Code Octal Value 8 Bit Code HGF_EDCBA 10 Bit Code RD abcdei_fghj 10 Bit Code RD abcdei_fghj Table 6 3 Valid Data Code Groups Part 1 of 9 Code Group Name Octet Value Octet Bits HGF EDCBA Current RD Current RD abcdei fghj abcdei fghj D0 0 00 000 00000 100111 0100 011000 1011 D1 0 01 000 00001 011101 0100 100010 1011 D2 0 02 000 00010 101101 0100 010010 1011 D3 0 0...

Page 664: ...00 100001 1011 D31 0 1F 000 11111 101011 0100 010100 1011 D0 1 20 001 00000 100111 1001 011000 1001 D1 1 21 001 00001 011101 1001 100010 1001 D2 1 22 001 00010 101101 1001 010010 1001 D3 1 23 001 00011 110001 1001 110001 1001 D4 1 24 001 00100 110101 1001 001010 1001 D5 1 25 001 00101 101001 1001 101001 1001 D6 1 26 001 00110 011001 1001 011001 1001 D7 1 27 001 00111 111000 1001 000111 1001 D8 1 2...

Page 665: ...111 101011 1001 010100 1001 D0 2 40 010 00000 100111 0101 011000 0101 D1 2 41 010 00001 011101 0101 100010 0101 D2 2 42 010 00010 101101 0101 010010 0101 D3 2 43 010 00011 110001 0101 110001 0101 D4 2 44 010 00100 110101 0101 001010 0101 D5 2 45 010 00101 101001 0101 101001 0101 D6 2 46 010 00110 011001 0101 011001 0101 D7 2 47 010 00111 111000 0101 000111 0101 D8 2 48 010 01000 111001 0101 000110...

Page 666: ...1 011000 1100 D1 3 61 011 00001 011101 0011 100010 1100 D2 3 62 011 00010 101101 0011 010010 1100 D3 3 63 011 00011 110001 1100 110001 0011 D4 3 64 011 00100 110101 0011 001010 1100 D5 3 65 011 00101 101001 1100 101001 0011 D6 3 66 011 00110 011001 1100 011001 0011 D7 3 67 011 00111 111000 1100 000111 0011 D8 3 68 011 01000 111001 0011 000110 1100 D9 3 69 011 01001 100101 1100 100101 0011 D10 3 6A...

Page 667: ...1 011101 0010 100010 1101 D2 4 82 100 00010 101101 0010 010010 1101 D3 4 83 100 00011 110001 1101 110001 0010 D4 4 84 100 00100 110101 0010 001010 1101 D5 4 85 100 00101 101001 1101 101001 0010 D6 4 86 100 00110 011001 1101 011001 0010 D7 4 87 100 00111 111000 1101 000111 0010 D8 4 88 100 01000 111001 0010 000110 1101 D9 4 89 100 01001 100101 1101 100101 0010 D10 4 8A 100 01010 010101 1101 010101 ...

Page 668: ... 010010 1010 D3 5 A3 101 00011 110001 1010 110001 1010 D4 5 A4 101 00100 110101 1010 001010 1010 D5 5 A5 101 00101 101001 1010 101001 1010 D6 5 A6 101 00110 011001 1010 011001 1010 D7 5 A7 101 00111 111000 1010 000111 1010 D8 5 A8 101 01000 111001 1010 000110 1010 D9 5 A9 101 01001 100101 1010 100101 1010 D10 5 AA 101 01010 010101 1010 010101 1010 D11 5 AB 101 01011 110100 1010 110100 1010 D12 5 A...

Page 669: ... 110001 0110 110001 0110 D4 6 C4 110 00100 110101 0110 001010 0110 D5 6 C5 110 00101 101001 0110 101001 0110 D6 6 C6 110 00110 011001 0110 011001 0110 D7 6 C7 110 00111 111000 0110 000111 0110 D8 6 C8 110 01000 111001 0110 000110 0110 D9 6 C9 110 01001 100101 0110 100101 0110 D10 6 CA 110 01010 010101 0110 010101 0110 D11 6 CB 110 01011 110100 0110 110100 0110 D12 6 CC 110 01100 001101 0110 001101...

Page 670: ...01010 1110 D5 7 E5 111 00101 101001 1110 101001 0001 D6 7 E6 111 00110 011001 1110 011001 0001 D7 7 E7 111 00111 111000 1110 000111 0001 D8 7 E8 111 01000 111001 0001 000110 1110 D9 7 E9 111 01001 100101 1110 100101 0001 D10 7 EA 111 01010 010101 1110 010101 0001 D11 7 EB 111 01011 110100 1110 110100 1000 D12 7 EC 111 01100 001101 1110 001101 0001 D13 7 ED 111 01101 101100 1110 101100 1000 D14 7 E...

Page 671: ...3 Valid Data Code Groups Part 9 of 9 Code Group Name Octet Value Octet Bits HGF EDCBA Current RD Current RD abcdei fghj abcdei fghj Table 6 4 Document Revision History Date and Document Version Changes Made Summary of Changes October 2007 v3 1 Updated Table 6 1 No change Formerly chapter 5 The chapter number changed due to the addition of the Stratix II GX Dynamic Reconfiguration chapter No conten...

Page 672: ...6 14 Altera Corporation Stratix II GX Device Handbook Volume 2 October 2007 Document Revision History ...

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