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anymore. Also test results would not correlate with other error counters such as
protocol testers anymore.
The high error ratio also serves as a trigger to perform an automatic re-
synchronization. So on one hand automatic pattern re-synchronization is desired
during receiver testing but it will be necessary to mask respectively do not account
the high error count (which was caused by the not synchronized error detector)
into the measurement. Side by side comparisons with other error counters show
that the loss of synchronization is usually caused by only one single bit error.
Error counting is performed in 200ms intervals. If the error ratio triggers a re-
synchronization of the error detector the current interval must not account into the
results. Furthermore, it is very likely that the previous 200ms interval(s) also
showed many errors due to lost synchronization but just did not raise the error
ratio to the specified trigger level. In later case, we check for errors in 201
th
ms and
if the errors are more than threshold, we discard these errors.
The measurement pauses until the ED successfully reached pattern sync again.
Furthermore, counters must be updated:
• The Re-Synchronization counter is incremented by one. This counter is also
incremented if high error ratio masking is turned off.
• In BER, “BER Comparison without PCIe3 SKPOS” and "Bit Comparison without
USB3.1 SKPOS" modes, one bit error shall be counted and the number of bits
is advance by one as well. As it would not be possible to identify the cause of
the synch loss, it may not be possible to account this into either errored 0’s or
1’s. However, displaying the re-synch counter also in BER mode is essential
and clarifies the mismatch of error count and sum of errored 0’s and 1’s.
• In "8B/10B Symbol Comparison" mode, the frame error counter and symbol
error counter are advanced by one. Since an error is counted also one received
frame is counted. The compared symbol counter is to be advanced by the block
length (in symbols) without fillers. Received symbols is incremented by pattern
length (in symbols) with fillers.
N O T E
For the applications (e.g. MIPI M-Phy) in which the synch loss is not caused by a
bit error, there is an option to count no errors instead of one when masking resynch
errors.
Other counters such as disparity error, illegal symbol counter and filler symbol
counter are discarded for 200ms during re-synchronization of the error detector.
Setting up the Error Detector
5
Agilent J-BERT N4903B High-Performance Serial BERT
219
Summary of Contents for J-BERT N4903B
Page 1: ...S Agilent J BERT N4903B High Performance Serial BERT User Guide s Agilent Technologies ...
Page 10: ...10 Agilent J BERT N4903B High Performance Serial BERT ...
Page 36: ...1 Planning the Test 36 Agilent J BERT N4903B High Performance Serial BERT ...
Page 60: ...2 Setting up External Instrument s 60 Agilent J BERT N4903B High Performance Serial BERT ...
Page 120: ...3 Setting up Patterns 120 Agilent J BERT N4903B High Performance Serial BERT ...
Page 360: ...6 Advanced Analysis 360 Agilent J BERT N4903B High Performance Serial BERT ...
Page 468: ...8 Jitter Tolerance Tests 468 Agilent J BERT N4903B High Performance Serial BERT ...
Page 524: ...9 Solving Problems 524 Agilent J BERT N4903B High Performance Serial BERT ...
Page 566: ...10 Customizing the Instrument 566 Agilent J BERT N4903B High Performance Serial BERT ...