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The error detector can then synchronize to the incoming signal. For PRBS, the
first received bits are used to seed the synchronization. If there is an errored
bit in this phase, the synchronization fails (bad burst).
For memory-based patterns, a unique 48-bit detect word is used for the
synchronization. This pattern should be available one time only in the pattern.
If the detect word is not found, synchronization fails (bad burst).
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If synchronization has been established, the received data is analyzed until the
signal at Gate In goes high, indicating the end of the burst. The data should
continue arriving at Data In slightly longer than the Gate In signal.
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In case of failed synchronization, the total burst counter and bad burst counter
are incremented. The bit counters (total count, error count, etc.) are not
incremented.
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At the end of the burst, the data is analyzed: the bits are counted, as are the
errors (total, errored 0s, errored 1s).
If the BER is higher than the
Burst Sync Threshold
(in the Pattern Sync Setup
dialog box), the burst is considered a bad burst, and the total burst count and
bad burst count are incremented.
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For good bursts, the total burst count is incremented, and the bits are analyzed
(bits and errors counted). The BER is also shown in the user interface.
Timing of the Signal at Gate In
The timing of the signal at Gate In is critical to the successful use of burst mode.
If the signal is not timed optimally, the resulting BER will be either too high, or the
sync ratio (good bursts / total bursts) will be too low.
The signal at Gate In has to start early enough for the error detector to get the
clock (the CDR settling time) and synchronize to the pattern. And it has to stop
before the burst ends, but should stay low as long as possible without hitting the
maximal length limitation (to extend the time where bits can be counted).
The following figure illustrates how the duration of the Gate In signal can influence
the bit count time (the time where bits are actually counted).
Data Input
Gate Input
CDR Settling Time
Synchronization Time
Bit Count Time
Burst
Gate Active
Valid after Gate
Begin Margin End Margin
Gate
Passive
Gate Active is the interval in which the Gate In signal is active.
Setting up the Error Detector
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Agilent J-BERT N4903B High-Performance Serial BERT
213
Summary of Contents for J-BERT N4903B
Page 1: ...S Agilent J BERT N4903B High Performance Serial BERT User Guide s Agilent Technologies ...
Page 10: ...10 Agilent J BERT N4903B High Performance Serial BERT ...
Page 36: ...1 Planning the Test 36 Agilent J BERT N4903B High Performance Serial BERT ...
Page 60: ...2 Setting up External Instrument s 60 Agilent J BERT N4903B High Performance Serial BERT ...
Page 120: ...3 Setting up Patterns 120 Agilent J BERT N4903B High Performance Serial BERT ...
Page 360: ...6 Advanced Analysis 360 Agilent J BERT N4903B High Performance Serial BERT ...
Page 468: ...8 Jitter Tolerance Tests 468 Agilent J BERT N4903B High Performance Serial BERT ...
Page 524: ...9 Solving Problems 524 Agilent J BERT N4903B High Performance Serial BERT ...
Page 566: ...10 Customizing the Instrument 566 Agilent J BERT N4903B High Performance Serial BERT ...