The following OS commands can be executed, even if either of the limit switches is active:
OS command 0 (Encoder register communication)
OS command 1 (iC-MU calibration mode)
OS command 3 (HRD streaming)
OS command 5 (Commutation offset detection with Method 2)
Homing modes
If the switch is active then Homing is only allowed in those modes that will take the axis away from the
activated switch. All those methods which try to move the axis further into the limit switch will raise an error.
The error raised depends on the limit switch being active:
For a positive limit switch the error raised will be PosLmAct
For a negative limit switch the error raised will be NegLmAct
3.1.4.4.2.4 Input actions
Use case: Interlock
When connecting different devices for a common process it’s often necessary to ensure the correct
order of operation. This can be done by routing the signals to the master but it comes at a cost for
reaction-time, data load and additional wiring. Input actions allow interlocking an operation directly at
the Drive to guarantee the correct order of the process.
Interlock (Disable Operation) Active Low - Level Triggered (10)
Clear bit 3 (eo) of controlword when the selected digital input is low.
This will cause the drive to transition into Operation disable state.
Interlock will remain active as long as the configured GPIO remains low and transitioning into OP Enabled
state will not be possible. Transitioning into OP Enabled state will only be possible when interlock is
deactivated by setting the GPIO input high. Bit 3 (interlock bit) of the
will also be
high when Interlock is active.
Fault reset (11)
Set bit 7 (fr) of controlword when the selected digital input is high.
Interlock (Fault Reaction) Active Low - Level Triggered (12)
Raises the fault “Interlck”, when the selected digital input is low.
This will cause the drive to transition into Fault Reaction State.
Interlock will remain active as long as the configured GPIO remains low and entering into OP Enabled state
will not be possible. If OP Enabled state is attempted to be entered while interlock is active, Interlck fault will
be raised again by the firmware. Transitioning into OP Enabled state will be possible when interlock is
deactivated by setting the configured GPIO input high. Bit 3 (interlock bit) of the
will also be high when Interlock is active.
Time Stamped Rising Edge - Edge Triggered (13)
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