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ICache and DCache behavior ..........................................................90
R2: Translation Table Base register.........................................................91
Register format..........................................................................91
R3:Domain Access Control register..........................................................91
Register format..........................................................................91
Access permissions and instructions .................................................91
R4 register ......................................................................................92
R5: Fault Status registers.....................................................................92
Access instructions......................................................................92
Register format..........................................................................92
Register bits .............................................................................92
Status and domain fields...............................................................93
R6: Fault Address register ....................................................................93
Access instructions......................................................................93
R7:Cache Operations register ................................................................94
Write instruction ........................................................................94
Cache functions .........................................................................94
Cache operation functions.............................................................95
Modified virtual address format (MVA) ..............................................96
Set/Way format .........................................................................96
Set/Way example .......................................................................96
Test and clean DCache instructions..................................................96
Test, clean, and invalidate DCache instruction ....................................97
R8:TLB Operations register...................................................................97
TLB operations ..........................................................................97
TLB operation instructions ............................................................97
Modified virtual address format (MVA) ..............................................98
R9: Cache Lockdown register ................................................................98
Cache ways...............................................................................98
Instruction or data lockdown register ...............................................99
Access instructions......................................................................99
Modifying the Cache Lockdown register.............................................99
Register format..........................................................................99
Cache Lockdown register L bits.......................................................99
Lockdown cache: Specific loading of addresses into a cache-way ............ 100
Cache unlock procedure ............................................................. 101
R10:TLB Lockdown register ................................................................ 101
Register format........................................................................ 101
P bit ..................................................................................... 101
Invalidate operation .................................................................. 101
Programming instructions............................................................ 102
Sample code sequence ............................................................... 102
R11 and R12 registers ....................................................................... 102
R13:Process ID register ..................................................................... 102
FCSE PID register...................................................................... 103
Summary of Contents for NS9215
Page 1: ...NS9215 Hardware Reference 90000847_C Release date 10 April 2008...
Page 3: ......
Page 4: ......
Page 26: ...26 Hardware Reference NS9215...
Page 44: ...P I N O U T 26 5 System clock 44 Hardware Reference NS9215 System clock drawing...
Page 52: ...P I N O U T 26 5 Power and ground 52 Hardware Reference NS9215...
Page 80: ...I O C O N T ROL M O D U L E Memory Bus Configuration register 80 Hardware Reference NS9215...
Page 136: ...WOR KI N G W I TH T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215...
Page 202: ...S Y S T E M C O N T RO L M OD U L E RTC Module Control register 202 Hardware Reference NS9215...
Page 354: ...E X T E R N A L D M A DMA Peripheral Chip Select register 354 Hardware Reference NS9215...
Page 472: ...R E A L TI M E C L O C K M O D U L E General Status register 472 Hardware Reference NS9215...
Page 512: ...TI M I NG Clock timing 512 Hardware Reference NS9215...
Page 515: ...PA CKA GING Processor Dimensions www digiembedded com 515...
Page 516: ...PA CKA GING Processor Dimensions 516 Hardware Reference NS9215...