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. . . . .

I 2 C   M A S T E R / S L A V E   I N T E R F A C E

Physical I2C bus

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447

I2C Master/Slave Interface

C

H

A

P

T

E

R

 

1

3

T

he I2C master/slave interface provides an interface between the ARM CPU and 

the I2C bus. 

The I2C master/slave interface basically is a parallel-to-serial and serial-to-parallel 
converter. The parallel data received from the ARM CPU has to be converted to an 
appropriate serial form to be transmitted to an external component using the I2C 
bus. Similarly, the serial data received from the I2C bus has to be converted to an 
appropriate parallel form for the ARM CPU. The I2C master interface also manages 
the interface timing, data structure, and error handling. 

Overview

The I2C module is designed to be a master and slave. The slave is active only when 
the module is being addressed during an I2C bus transfer; the master can arbitrate 
for and access the I2C bus only when the bus is free (idle) — therefore, the master 
and slave are mutually exclusive.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

P h y s i c a l   I

2

C   b u s

The physical I

2

C bus consists of two open-drain signal lines: serial data (SDA) and 

serial clock (SCL). Pullup resistors are required; see the standard I

2

C bus 

specification for the correct value for the application. Each device connected to the 
bus is software-addressable by a unique 7- or 10-bit address, and a simple 
master/slave relationship exists at all times. 

A master can operate as a master-transmitter (writes)) or a master-receiver 
(reads). The slaves respond to the received commands accordingly:
•

In transmit mode (slave is read), the host interface receives character-based 
parallel data from the ARM. The module converts the parallel data to serial 
format and transmits the serial data to the I

2

C bus.

•

In receive mode (slave is written to), the I

2

C bus interface receives 8-bit-

based serial data from the I

2

C bus. The module converts the serial data to 

parallel format and interrupts the host. The host’s interrupt service routine 
reads the parallel data from the data register inside the I

2

C module. The 

serial data stream synchronization and throttling are done by modulating the 

Summary of Contents for NS9215

Page 1: ...NS9215 Hardware Reference 90000847_C Release date 10 April 2008...

Page 2: ...nge without notice and does not represent a commitment on the part of Digi International Digi provides this document as is without warranty of any kind either expressed or implied including but not li...

Page 3: ......

Page 4: ......

Page 5: ...l and Status registers 53 Register address map 53 GPIO Configuration registers 55 GPIO configuration options 55 GPIO Configuration Register 0 56 GPIO Configuration Register 1 56 GPIO Configuration Reg...

Page 6: ...gister 3 73 GPIO Status registers 74 GPIO Status Register 1 74 GPIO Status Register 2 75 GPIO Status Register 3 76 Memory Bus Configuration register 76 C h a p t e r 3 W o r k i n g w i t h t h e C P...

Page 7: ...rmat 96 Set Way example 96 Test and clean DCache instructions 96 Test clean and invalidate DCache instruction 97 R8 TLB Operations register 97 TLB operations 97 TLB operation instructions 97 Modified...

Page 8: ...ts Priority encoding of fault status 111 First level descriptor bit assignments Interpreting first level descriptor bits 1 0 111 Section descriptor 111 Section descriptor format 111 Section descriptor...

Page 9: ...sabling the MMU 126 TLB structure 126 Caches and write buffer 127 Cache features 127 Write buffer 128 Enabling the caches 128 ICache I and M bit settings 129 ICache page table C bit settings 129 R1 re...

Page 10: ...ture decoder function 145 How the quadrature decoder counter works 146 Provides input signals 146 Monitors how far the encoder has moved 147 Digital filter 147 Testing signals 147 Timer support 147 In...

Page 11: ...laneous System Configuration and Status register 184 PLL Configuration register 186 PLL frequency formula 186 Active Interrupt Level ID Status register 187 Power Management 187 AHB Bus Activity Status...

Page 12: ...ansfers with zero wait states 212 Burst of zero wait states with fixed length 213 Burst of two wait states with fixed length 213 Asynchronous page mode read 214 Asynchronous page mode read Timing and...

Page 13: ...c Memory Active to Precharge Command Period register 239 Dynamic Memory Self refresh Exit Time register 240 Dynamic Memory Last Data Out to Active Time register 240 Dynamic Memory Data in to Active Co...

Page 14: ...Power down mode 267 Transferring a frame to system memory 268 Receive buffer descriptor format 268 Receive buffer descriptor format description 268 Receive buffer descriptor field definitions 269 Tra...

Page 15: ...ent Read Data register 298 MII Management Indicators register 299 Station Address registers 300 Station Address Filter register 301 RegisterHash Tables 302 HT1 302 HT2 303 Statistics registers 303 Com...

Page 16: ...ster 2 311 Carry Register 1 Mask register 312 Carry Register 2 Mask register 314 RX_A Buffer Descriptor Pointer register 315 RX_B Buffer Descriptor Pointer register 315 RX_C Buffer Descriptor Pointer...

Page 17: ...ess Mask Register 4 330 Multicast Low Address Mask Register 5 330 Multicast Low Address Mask Register 6 330 Multicast Low Address Mask Register 7 330 Multicast High Address Mask Register 0 330 Multica...

Page 18: ...g 344 REQ signal 344 DONE signal 345 Special circumstances 345 Static RAM chip select configuration 345 Static ram chip select configuration 345 Control and Status registers 346 Register address map 3...

Page 19: ...trol 14 I 365 Control 13 L 365 Control 12 F 365 Control 11 0 366 Status 15 0 366 Transmit DMA example 367 Process 367 Visual example 368 Control and status register address maps 368 UART A register ad...

Page 20: ...based flow control XON XOFF 388 Example configuration 388 Forced character transmission 388 Force character transmission procedure 389 Collecting feedback 389 ARM wakeup on character recognition 389 E...

Page 21: ...acked bit cell boundaries 419 NRZ and NRZI data encoding 419 Biphase data encoding 419 DPLL operation Adjustment ranges and output clocks 419 NRZ and NRZI encoding 420 Biphase Level encoding 420 Bipha...

Page 22: ...onfiguration register 439 Clock Generation register 440 Register programming steps 441 Interrupt Enable register 441 Interrupt Status register 442 SPI timing characteristics 443 SPI master timing diag...

Page 23: ...458 C h a p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 RTC functionality 459 RTC configuration and status registers 460 Register address map 460 RTC General Control register 460 12 24 Hour r...

Page 24: ...2 bit 490 SDRAM load mode 491 SDRAM refresh mode 492 Clock enable timing 493 Values in SRAM timing diagrams 494 Static RAM read cycles with 0 wait states 495 Static RAM asynchronous page mode read WTP...

Page 25: ...dded com 25 Clock timing 511 System PLL reference clock timing 511 C h a p t e r 1 7 P a c k a g i n g 513 Package 513 Processor Dimensions 514 C h a p t e r 1 8 C h a n g e l o g 517 Revision B 517 R...

Page 26: ...26 Hardware Reference NS9215...

Page 27: ...cription Pin Pin number assigned for a specific I O signal Signal Pin name for each I O signal Some signals have multiple function modes and are identified accordingly The mode is configured through f...

Page 28: ...addr 19 U I O 4 Address bus GENID 10 T11 addr 18 U I O 4 Address bus GENID 9 U12 addr 17 U I O 4 Address bus GENID 8 T10 addr 16 U I O 4 Address bus GENID 7 R9 addr 15 U I O 4 Address bus GENID 6 U11...

Page 29: ...U I O 4 Data bus D1 data 17 U I O 4 Data bus E2 data 16 U I O 4 Data bus H4 data 15 gpio 31 b U I O 4 Data bus G3 data 14 gpio 30 U I O 4 Data bus G4 data 13 gpio 29 U I O 4 Data bus G5 data 12 gpio...

Page 30: ...dy_cs3 A3 cs 6 O 4 Chip select 6 st_cs3 A4 cs 5 O 4 Chip select 5 dy_cs2 C5 cs 4 O 4 Chip select 4 st_cs2 B5 cs 3 O 4 Chip select 3 dy_cs1 B6 cs 2 O 4 Chip select 2 st_cs1 Flash boot D6 cs 1 O 4 Chip...

Page 31: ...he primary GPIO pin has precedence and will be used The I2 C module must be held in reset until the GPIO assigned to I2 C has been configured D12 txd 2 gpio 46 U I O 2 TX data 2 C12 txd 1 gpio 45 U I...

Page 32: ...3 gpio 1 4 Reserved J17 gpio 2 U I O 2 0 DSR UART A 1 Ext Int 1 2 PIC_0_GEN_IO 2 I O 3 gpio 2 4 Reserved J16 gpio 3 U I O 2 0 RXD UART A 1 Ext DMA Pden Ch 0 2 PIC_0_GEN_IO 3 I O 3 gpio 3 4 SPI RXD du...

Page 33: ...IC_DBG_CLK O F13 gpio 11 U I O 2 0 RXD UART C 1 Ext DMA Pden Ch 1 2 Ext Int Ch 2 dup 3 gpio 11 4 SPI RXD boot F17 gpio 12 U I O 4 0 RXC RI UART C 1 I2 C SDAa 2 reset_done 3 gpio 12 4 SPI CLK dup F15 g...

Page 34: ...ART B 2 EXT INT CH 3 dup 3 gpio 19 B1 gpio 20 U I O 4 0 data 4 1 RI UART B 2 Ext DMA Done Ch 0 dup 3 gpio 20 E3 gpio 21 U I O 4 0 data 5 1 RTS RS485 Control UART B 2 Ext DMA Pden Ch 0 dup 3 gpio 21 D2...

Page 35: ...D 2 PIC_1_GEN_IO 3 I O 3 gpio 29 G3 gpio 30 U I O 4 0 data 14 1 TXC DTR UART D 2 Reserved 3 gpio 30 H4 gpio 31 U I O 4 0 data 15 1 TXD UART D 2 Reserved 3 gpio 31 A12 gpio 32 U I O 2 0 Ethernet MII M...

Page 36: ...O 7 I O dup 2 Reserved 3 gpio 39 D16 gpio 40 U I O 2 0 Ethernet MII RXD 2 1 PIC_1_GEN_IO 0 I O dup 2 Reserved 3 gpio 40 E17 gpio 41 U I O 2 0 Ethernet MII RXD 3 1 PIC_1_GEN_IO 1 I O dup 2 Reserved 3 g...

Page 37: ...rved 3 gpio 49 C11 gpio 50 U I O 2 0 Ethernet MII PHY Int 1 PIC_1_CLK I 2 PIC_1_CLK O 3 gpio 50 E10 gpio 51 U I O 2 0 DCD UART B dup 1 PIC_0_BUS_1 8 I O 2 PIC_1_BUS_1 8 I O 3 gpio 51 D10 gpio 52 U I O...

Page 38: ...2 PIC_1_BUS_1 16 I O 3 gpio 59 R6 gpio 60 U I O 2 0 CTS UART D dup 1 PIC_0_BUS_1 17 I O 2 PIC_1_BUS_1 17 I O 3 gpio 60 P6 gpio 61 U I O 2 0 DSR UART D dup 1 PIC_0_BUS_1 18 I O 2 PIC_1_BUS_1 18 I O 3 g...

Page 39: ...IC_1_CAN_TXD O dup 3 gpio 69 N10 gpio 70 U I O 2 0 PIC_0_GEN_IO 2 I O dup 1 PIC_1_GEN_IO 2 I O 2 PWM Ch 0 3 gpio 70 P11 gpio 71 U I O 2 0 PIC_0_GEN_IO 3 I O dup 1 PIC_1_GEN_IO 3 I O 2 PWM Ch 1 3 gpio...

Page 40: ...in Ch 5 3 gpio 79 R17 gpio 80 U I O 2 0 PIC_0_BUS_0 0 I O 1 PIC_1_BUS_0 0 I O 2 Ext Timer Event in Ch 6 dup 3 gpio 80 P17 gpio 81 U I O 2 0 PIC_0_BUS_0 1 I O 1 PIC_1_BUS_0 1 I O 2 Ext Timer Event in C...

Page 41: ...mer Event Out Ch 5 3 gpio 89 H16 gpio 90 U I O 2 0 PIC_0_BUS_0 10 I O 1 PIC_1_BUS_0 10 I O 2 Ext Timer Event Out Ch 6 3 gpio 90 H15 gpio 91 U I O 2 0 PIC_0_BUS_0 11 I O 1 PIC_1_BUS_0 11 I O 2 Ext Time...

Page 42: ...1_BUS_1 3 I O 2 PIC_1_CAN_TXD O dup 3 gpio 99 D8 gpio 100 U I O 2 0 PIC_0_BUS_1 4 I O 1 PIC_1_BUS_1 4 I O 2 PWM Ch 4 3 gpio 100 C8 gpio 101 U I O 2 0 PIC_0_BUS_1 5 I O 1 PIC_1_BUS_1 5 I O 2 Ext Int Ch...

Page 43: ...s the I2C_SDA signal in this case the I2C_SDA signal is driven low while in reset then driven active high after end of reset until software configures this pin for the I2C function Pin Signal U D I O...

Page 44: ...P I N O U T 26 5 System clock 44 Hardware Reference NS9215 System clock drawing...

Page 45: ...the following connection changes can be made S y s t e m m o d e v N3 M4 bat_vdd_reg tie to 1 8V 32 788kHz crystal load capacitors tie to N3 M4 1 8V N4 bat_vdd tie to 3 3V R1 aux_comp tie to ground P...

Page 46: ...test 0 0 1 manufacturing test 0 1 0 manufacturing test 0 1 1 normal operation boundary scan enabled POR disabled 1 0 0 normal operation boundary scan enabled POR enabled 1 0 1 board test mode all out...

Page 47: ...her Strappings Endianess YES NO NO NO GPIO Configuration YES NO NO NO Other ASIC Registers YES YES YES YEs POR trips when voltageonL3 drops below 2 74V 2 97V PORdisable as encodedonmodepins NS9215 Cor...

Page 48: ...Pin Signal U D I O OD Description N14 tdi U I Test data in N15 tdo O 2 Test data out T17 tms U I Test mode select R16 trst_n U I Test mode reset For normal operation this pin is tied to ground or pull...

Page 49: ...C input 0 T3 vin1_adc I ADC input 1 R5 vin2_adc I ADC input 2 U2 vin3_adc I ADC input 3 T4 vin4_adc I ADC input 4 U3 vin5_adc I ADC input 5 T5 vin6_adc I ADC input 6 U4 vin7_adc I ADC input 7 P4 agnd_...

Page 50: ...ference POR reference trip voltage 2 74V min 2 97V max T1 por_early_reference POR early power loss voltage 1 19V min 1 28V max N4 bat_vdd Battery VDD 3 0V R1 aux_comp Auxiliary analog comparator input...

Page 51: ...drawing on page 45 P o w e r a n d g r o u n d N4 Bat_vdd tie to 3 3V R1 aux_comp tie to ground N3 M4 bat_vdd_reg tie to ground P2 x1_rtc_osc tie to ground R2 x2_rtc_osc leave open Pin Signal E7 E11 G...

Page 52: ...P I N O U T 26 5 Power and ground 52 Hardware Reference NS9215...

Page 53: ...c required to accomplish this task System memory bus I O control The registers in this section control these system memory I O configuration options System chip select options used to select which chi...

Page 54: ...Configuration Register 16 R W 0x18181818 A090_2044 GPIO Configuration Register 17 R W 0x18181818 A090_2048 GPIO Configuration Register 18 R W 0x18181818 A090_204C GPIO Configuration Register 19 R W 0...

Page 55: ...GPIO pins to NS9215 Address Description Access Reset value Bit s Mnemonic Description D07 06 Reserved N A D05 03 FUNC Use these bits to select the function you want to use For a definition of each fu...

Page 56: ...Reset Description D31 24 R W GPIO3 0x18 GPIO 3 configuration D23 16 R W GPIO2 0x18 GPIO 2 configuration D15 08 R W GPIO1 0x18 GPIO 1 configuration D07 00 R W GPIO0 0x18 GPIO 0 configuration 13 12 11...

Page 57: ...scription D31 24 R W GPIO11 0x18 GPIO 11 configuration D23 16 R W GPIO10 0x18 GPIO 10 configuration D15 08 R W GPIO9 0x18 GPIO 9 configuration D07 00 R W GPIO8 0x18 GPIO 8 configuration 13 12 11 10 9...

Page 58: ...escription D31 24 R W GPIO19 0x00 GPIO 19 configuration D23 16 R W GPIO18 0x00 GPIO 18 configuration D15 08 R W GPIO17 0x00 GPIO 17 configuration D07 00 R W GPIO16 0x00 GPIO 16 configuration 13 12 11...

Page 59: ...cription D31 24 R W GPIO27 0x00 GPIO 27 configuration D23 16 R W GPIO26 0x00 GPIO 26 configuration D15 08 R W GPIO25 0x00 GPIO 25 configuration D07 00 R W GPIO24 0x00 GPIO 24 configuration 13 12 11 10...

Page 60: ...escription D31 24 R W GPIO35 0x18 GPIO 35 configuration D23 16 R W GPIO34 0x18 GPIO 34 configuration D15 08 R W GPIO33 0x18 GPIO 33 configuration D07 00 R W GPIO32 0x18 GPIO 32 configuration 13 12 11...

Page 61: ...scription D31 24 R W GPIO43 0x18 GPIO 43 configuration D23 16 R W GPIO42 0x18 GPIO 42 configuration D15 08 R W GPIO41 0x18 GPIO 41 configuration D07 00 R W GPIO40 0x18 GPIO 40 configuration 13 12 11 1...

Page 62: ...Description D31 24 R W GPIO51 0x18 GPIO 51 configuration D23 16 R W GPIO50 0x18 GPIO 50 configuration D15 08 R W GPIO49 0x18 GPIO 49 configuration D07 00 R W GPIO48 0x18 GPIO 48 configuration 13 12 11...

Page 63: ...scription D31 24 R W GPIO59 0x18 GPIO 59 configuration D23 16 R W GPIO58 0x18 GPIO 58 configuration D15 08 R W GPIO57 0x18 GPIO 57 configuration D07 00 R W GPIO56 0x18 GPIO 56 configuration 13 12 11 1...

Page 64: ...Description D31 24 R W GPIO67 0x18 GPIO 67 configuration D23 16 R W GPIO66 0x18 GPIO 66 configuration D15 08 R W GPIO65 0x18 GPIO 65 configuration D07 00 R W GPIO64 0x18 GPIO 64 configuration 13 12 11...

Page 65: ...scription D31 24 R W GPIO75 0x18 GPIO 75 configuration D23 16 R W GPIO74 0x18 GPIO 74 configuration D15 08 R W GPIO73 0x18 GPIO 73 configuration D07 00 R W GPIO72 0x18 GPIO 72 configuration 13 12 11 1...

Page 66: ...Description D31 24 R W GPIO83 0x18 GPIO 83 configuration D23 16 R W GPIO82 0x18 GPIO 82 configuration D15 08 R W GPIO81 0x18 GPIO 81 configuration D07 00 R W GPIO80 0x18 GPIO 80 configuration 13 12 11...

Page 67: ...scription D31 24 R W GPIO91 0x18 GPIO 91 configuration D23 16 R W GPIO90 0x18 GPIO 90 configuration D15 08 R W GPIO89 0x18 GPIO 89 configuration D07 00 R W GPIO88 0x18 GPIO 88 configuration 13 12 11 1...

Page 68: ...ption D31 24 R W GPIO99 0x18 GPIO 99 configuration D23 16 R W GPIO98 0x18 GPIO 98 configuration D15 08 R W GPIO97 0x18 GPIO 97 configuration D07 00 R W GPIO96 0x18 GPIO 96 configuration 13 12 11 10 9...

Page 69: ...1 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 GPIO_A3 GPIO_A2 GPIO_A1 GPIO_A0 Bit s Access Mnemonic Reset Description D31 24 R W GPIO_A3 0x18 GPIO_A 3 configuration D2...

Page 70: ...bit D03 R W GPIO3 0 GPIO 3 control bit D04 R W GPIO4 0 GPIO 4 control bit D05 R W GPIO5 0 GPIO 5 control bit D06 R W GPIO6 0 GPIO 6 control bit D07 R W GPIO7 0 GPIO 7 control bit D08 R W GPIO8 0 GPIO...

Page 71: ...R W GPIO34 0 GPIO 34 control bit D03 R W GPIO35 0 GPIO 35 control bit D04 R W GPIO36 0 GPIO 36 control bit D05 R W GPIO37 0 GPIO 37 control bit D06 R W GPIO38 0 GPIO 38 control bit D07 R W GPIO39 0 GP...

Page 72: ...Access Mnemonic Reset Description D00 R W GPIO64 0 GPIO 64 control bit D01 R W GPIO65 0 GPIO 65 control bit D02 R W GPIO66 0 GPIO 66 control bit D03 R W GPIO67 0 GPIO 67 control bit D04 R W GPIO68 0...

Page 73: ...bit D29 R W GPIO93 0 GPIO 93 control bit D30 R W GPIO94 0 GPIO 94 control bit D31 R W GPIO95 0 GPIO 95 control bit Bit s Access Mnemonic Reset Description Bit s Access Mnemonic Reset Description D00...

Page 74: ...ed GPIO 37 status bit D06 R GPIO38 Undefined GPIO 38 status bit D07 R GPIO39 Undefined GPIO 39 status bit D08 R GPIO40 Undefined GPIO 40 status bit D09 R GPIO41 Undefined GPIO 41 status bit D10 R GPIO...

Page 75: ...atus bit D04 R GPIO68 Undefined GPIO 68 status bit D05 R GPIO69 Undefined GPIO 69 status bit D06 R GPIO70 Undefined GPIO 70 status bit D07 R GPIO71 Undefined GPIO 71 status bit D08 R GPIO72 Undefined...

Page 76: ...R GPIO93 Undefined GPIO 93 status bit D30 R GPIO94 Undefined GPIO 94 status bit D31 R GPIO95 Undefined GPIO 95 status bit Bit s Access Mnemonic Reset Description Bit s Access Mnemonic Reset Descripti...

Page 77: ...0 Controls which system memory chip select is routed to CS1 000 dy_cs_0 default 001 dy_cs_1 010 dy_cs_2 011 dy_cs_3 100 st_cs_0 101 st_cs_1 110 st_cs_2 111 st_cs_3 D08 06 R W CS2 0x5 Controls which sy...

Page 78: ...st_cs_1 110 st_cs_2 111 st_cs_3 D20 18 R W CS6 0x7 Controls which system memory chip select is routed to CS6 000 dy_cs_0 001 dy_cs_1 010 dy_cs_2 011 dy_cs_3 100 st_cs_0 101 st_cs_1 110 st_cs_2 111 st...

Page 79: ...9 D25 R W APUDIS 0x0 Address bus pullup control Applicable only to address associated with hardware strapping 0 Enable pullup resistors 1 Disable pullup resistors Note Bits 27 24 are output and contro...

Page 80: ...I O C O N T ROL M O D U L E Memory Bus Configuration register 80 Hardware Reference NS9215...

Page 81: ...sets allowing you to trade off between high performance and high code density The processor includes features for efficient execution of Java byte codes providing Java performance similar to JIT but...

Page 82: ...chieve maximum performance with the minimum number of instructions The majority of instructions are executed in a single cycle Thumb instruction set The Thumb instruction set is simpler than the ARM i...

Page 83: ...A In the AMBA domain Physical address PA Address manipulation example This is an example of the address manipulation that occurs when the ARM926EJ S core requests an instruction 1 The ARM926EJ S core...

Page 84: ...abbreviations This table lists the terms and abbreviations used in the CP15 registers and explanations Cond 1 1 1 0 1 1 1 1 1 L Opcode _1 Opcode _2 CRn CRm Rd 31 28 27 26 25 24 23 21 20 19 16 15 12 1...

Page 85: ...he V bit is set to 0 at reset if the VINITHI signal is low and set to 1 if the VINITHI signal is high Register Reads Writes 0 ID code based on opcode_2 value Unpredictable 0 Cache type based on opcode...

Page 86: ...access the ID code register by reading CP15 register R0 with the opcode_2 field set to any value other than 1 or 2 Note this example MRC p15 0 Rd c0 c0 0 3 7 returns ID This is the contents of the ID...

Page 87: ...ype and specifies whether the cache supports lockdown and how it is cleaned Ctype encoding is shown below all unused values are reserved Value 0b1110 Method Writeback Cache cleaning Register 7 operati...

Page 88: ...on Size Determines the cache size in conjunction with the M bit The M bit is 0 for DCache and ICache The size field is bits 21 18 for the DCache and bits 9 6 for the ICache The minimum size of each ca...

Page 89: ...the T is set when load instructions change the PC 0 Loads to PC set the T bit 1 Loads to PC do not set the T bit 14 RR bit Replacement strategy for ICache and DCache 0 Random replacement 1 Round robi...

Page 90: ...Bits Name Function Cache MMU Behavior ICache disabled Enabled or disabled All instruction fetches are from external memory AHB ICache enabled Disabled All instruction fetches are cachable with no pro...

Page 91: ...ister R3 is the Domain Access Control register and consists of 16 two bit fields Reading from R3 returns the value of the Domain Access Control register Writing to R3 writes the value of the Domain Ac...

Page 92: ...determined by the opcode_2 value See MemoryManagement Unit MMU beginning on page 105 for the fault type encoding Access instructions Access the FSRs using these instructions MRC p15 0 Rd c5 c0 0 read...

Page 93: ...aborts it is updated also for alignment faults and external aborts that occur while the MMU is disabled Writing R6 sets the Fault Address register to the value of the data written This is useful for d...

Page 94: ...modified virtual address Invalidates a single cache line discarding any dirty data Clean single data entry using either index or modified virtual address Writes the specified DCache line to main memor...

Page 95: ...the MCR instruction completes and the IRQ or FIRQ handler is entered as normal The return link in R14_irq or R14_fiq contains the address of the MCR instruction plus eight so the typical instruction...

Page 96: ...line results in the following A log2 associativity log24 2 S log2 NSETS where NSETS cache size in bytes associativity line length in bytes NSETS 16384 4 32 128 Result S log2 128 7 Test and clean DCac...

Page 97: ...n s r e g i s t e r Register R8 is a write only register that controls the translation lookaside buffer TLB There is a single TLB used to hold entries for both data and instructions The TLB is divided...

Page 98: ...ccess this register using CRm 0 Cache ways The Cache Lockdown register uses a cache way based locking scheme format C that allows you to control each cache way independently These registers allow you...

Page 99: ...of the ICache Register format This is the format for the Cache Lockdown register Cache Lockdown register L bits This table shows the format of the Cache Lockdown register L bits All cache ways are av...

Page 100: ...eady locked cache way 4 Ensure that the data instructions that are to be locked down are in a cachable area of memory 5 Be sure that the data instructions that are to be locked down are not already in...

Page 101: ...ight entries see the discussion of the TLB structure in TLB structure beginning on page 126 for more information Register format P bit When writing the TLB Lockdown register the value in the P bit D0...

Page 102: ...the address to be locked down MCR p15 0 r1 c8 c7 1 invalidate TLB single entry to ensure that LockAddr is not already in the TLB MRC p15 0 r0 c10 c0 0 read the lockdown register ORR r0 r0 1 set the pr...

Page 103: ...ation FCSE translation is not applied for addresses used for entry based cache or TLB maintenance operations For these operations VA MVA Access instructions Use these instructions to access the FCSE P...

Page 104: ...15 to provides device specific test and debug operations in ARM926EJ S processors Use of this register currently is reserved J a z e l l e J a v a The ARM926EJ S processor has ARM s embedded Jazelle J...

Page 105: ...FFT State space servo control M e m o r y M a n a g e m e n t U n i t M M U The MMU provides virtual memory features required by systems operating on platforms such as WindowsCE or Linux A single set...

Page 106: ...latter two cases the access permission attributes are ignored There are 16 domains which are configured using R3 Domain Access Control register see R3 Domain Access Control register on page 91 Transla...

Page 107: ...ess of the base of the translation table maintained in main memory This base address must be on a 16 KB boundary R3 DomainAccessControl register 31 0 Comprises 16 two bit fields Each field defines the...

Page 108: ...pped access Page mapped accesses are for large pages small pages and tiny pages The translation process always begins in the same way with a level one fetch A section mapped access requires only a lev...

Page 109: ...table Section base Indexed by modified virtual address bits 19 0 4096 entries 1 MB Section Large page Indexed by modified virtual address bits 15 0 Large page base Coarse page table Coarse page table...

Page 110: ...criptors The page table descriptors provide the base address of a page table that contains second level descriptors There are two page table sizes Coarse page tables which have 256 entries and split t...

Page 111: ...rpreting the access permission bits 9 9 11 9 SHOULD BE ZERO 8 5 8 5 8 5 Domain control bits 4 4 4 Must be 1 3 2 Bits C and B indicate whether the area of memory mapped by this page is treated as write...

Page 112: ...orresponding bits of the physical address for a section 19 12 Always written as 0 11 10 Specify the access permissions for this section 09 Always written as 0 8 5 Specifies one of the 16 possible doma...

Page 113: ...escriptor format Fine page table descriptor bit description Translating section references This figure illustrates the complete section translation sequence Fine page table base address SBZ Domain 1 1...

Page 114: ...ge descriptor or is invalid A large page descriptor provides the base address of a 64 KB block of memory A small page descriptor provides the base address of a 4 KB block of memory 31 14 13 0 Translat...

Page 115: ...e as shown in this table Note Tiny pages do not support subpage permissions and therefore have only one set of access permission bits Bits Large Small Tiny Description 31 16 31 12 31 10 Form the corre...

Page 116: ...der six bits of the page index and low order six bits of the fine page table overlap Each fine page table entry for a large page must be duplicated 64 times 31 14 13 0 Translation base 1 Translation t...

Page 117: ...page must be duplicated four times 31 14 13 0 Translation base 1 Translation table base 31 14 13 0 Translation base 2 Table index 0 0 31 2019 0 Table index Page index First level descriptor 31 0 Coar...

Page 118: ...ges of small and large pages If during a page table walk a small or large page has a different subpage permission only the subpage being accessed is written into the TLB For example a 16 KB large page...

Page 119: ...echanisms of the MMU detect the conditions that produce these faults If a fault is detected as a result of a memory access the MMU aborts the access and signals the fault condition to the CPU core The...

Page 120: ...fetches The Instruction Fault Status register can be updated for instruction prefetch operations MCR p15 0 Rd c7 c13 1 Fault Address register FAR For load and store instructions that can involve the...

Page 121: ...main are defined to specify access permissions Interpreting access permission bits This table shows how to interpret the access permission AP bits and how the interpretation depends on the R and S bit...

Page 122: ...access faults is different for sections and pages The next figure shows the sequence for both types of access AP S R Privileged permissions User permissions 0 0 0 0 No access No access 0 0 1 0 Read on...

Page 123: ...e address is not halfword aligned irrespective of whether the MMU is enabled An alignment fault is not generated on any instruction fetch or byte access Modified virtual address Check address alignmen...

Page 124: ...s Control register The two bits of the specified domain are then checked for access permissions as described in Interpreting access permission bits on page 121 The domain is checked when the level one...

Page 125: ...borted in this way however These accesses can be aborted externally Page walks Noncached reads Nonbuffered writes Noncached read lock write SWP sequence For a read lock write SWP sequence the write is...

Page 126: ...bled then disabled then subsequently re enabled the contents of the TLB are preserved If these are now invalid the TLB must be invalidated before re enabling the MMU see R8 TLB Operations register on...

Page 127: ...must be used to remove any cached copies of the level one descriptor This is required regardless of the type of level one descriptor section level two page reference or fault If any of the subpage per...

Page 128: ...Cache Regions of virtual memory The latter allows DCache coherency to be efficiently maintained when small code changes occur for example for self modifying code and changes to exception vectors Write...

Page 129: ...cachable or noncachable depending on the page descriptor C bit see ICache page table C bit settings on page 129 and protection checks are performed All addresses are remapped from VA to PA depending o...

Page 130: ...0 Noncachable nonbufferable DCache disabled Read from external memory Write as a nonbuffered store s to external memory DCache is not updated 0 1 Noncachable bufferable DCache disabled Read from exter...

Page 131: ...N G W I TH T H E C P U Cache MVA and Set Way formats www digiembedded com 131 Generic virtually indexed virtually addressed cache 0 0 1 2 3 4 5 6 7 n TAG 1 2 3 0 1 2 m m m m Hit Read data Tag Index W...

Page 132: ...sociativity The ARM926EJ S caches are 4 way associative The range of tags addressed by the index defines a way The number of tags is a way is the number of sets NSETS This table shows values of S and...

Page 133: ...of the buffer are discarded flushed In situations on which the contents of the prefetch buffer might become invalid during a sequence of sequential instruction fetches by the processor core for examp...

Page 134: ...idated IMB operation Use this procedure to ensure consistency between data and instruction sides 1 Clean the DCache If the cache contains cache lines corresponding to write back regions of memory it m...

Page 135: ...modifying code is executed see Self modifying code on page 133 Sample IMB sequences These sequences correspond to steps 1 4 in IMB operation clean loop MRC p15 0 r15 c7 c10 3 clean entire dcache using...

Page 136: ...WOR KI N G W I TH T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215...

Page 137: ...l purpose timers counters Interrupt controller Multiple configuration and status registers System Sleep Wake up processor B u s i n t e r c o n n e c t i o n The AMBA AHB bus protocol uses a central m...

Page 138: ...PU has immediate access to external memory through slave port 0 on the memory controller If CPU access is to one of the peripherals on the main bus however the main arbiter will arbitrate the access M...

Page 139: ...r that owns the address control bus can use the data bus and continues to own that data bus until the transaction completes Note If a master is assigned more than one request grant channel these chann...

Page 140: ...xt round of arbitration The master eventually is granted access to the bus to try the transfer again Note The arbiter automatically blocks bus requests with addresses directed at a SPLITting slave unt...

Page 141: ...ote that the external memory chip select ranges can be reset after powerup The table shows the default powerup values you can change the ranges by writing to the BASE and MASK registers see System Mem...

Page 142: ...tware must write to the Software Watchdog Timer register before it expires When the timer does timeout the system is preconfigured to generate an IRQ an FIQ or a RESET to restart the entire system 0x7...

Page 143: ...event The divisor options are 2 4 6 16 32 62 128 or 256 If an external pulse is used the frequency must be less than one half the system memory clock frequency GPTC characteristics Each GPTC can meas...

Page 144: ...an external event and interrupt the CPU Compare mode Interrupt the CPU when the counter value is equal to the Match register B a s i c P W M f u n c t i o n Any of the timer counters can be configured...

Page 145: ...external device rate of rotation and the direction of rotation Example applications are robotic axles for feedback control mechanical knobs to determine user input and in computer mice to determine di...

Page 146: ...input signals A quadrature encoder provides a pair of signals in phase and quad phase with opposite polarities and a 90 degree phase shift Decode these signals to create an algorithm to determine the...

Page 147: ...ram shows a typical application of the quadrature decoder counter Digital filter To ensure the precision and quality of the quadrature decoder counter a digital filter rejects noise on the incoming qu...

Page 148: ...or FIQ interrupts are more efficient because a context save is not required Note The interrupt source assigned to the FIQ must be assigned to the highest priority which is 0 IRQ interrupts IRQ interru...

Page 149: ...iced allowing lower priority interrupts to become active The write value to the ISADDR register must be the level of the interrupt being serviced Valid values are 0 31 The priority encoder block enabl...

Page 150: ...nterrupt 7 UART A Interrupt 8 UART B Interrupt 9 UART C Interrupt 10 UART D Interrupt 11 SPI Interrupt 12 Reserved 13 Reserved 14 ADC Interrupt 15 Early Power Loss Interrupt 16 I2 C Interrupt 17 RTC I...

Page 151: ...e serviced 6 The CPU executes the interrupt service routine 7 The CPU clears the source of the current interrupt 8 The CPU disables the IRQ and restores the workspace 9 If IRQ the CPU writes the level...

Page 152: ...the internal pullup NR 1 Clk Out CPU clock CPU clock AHB clock CCSel 1 CCSel 0 6 299 8272 149 9136 74 9568 74 9568 7 256 9947 128 4975 64 2487 64 2487 8 224 8704 112 4352 56 2176 56 2176 9 199 8848 99...

Page 153: ...bit If booting from SPI 00 Reserved 01 8 bit addressing 10 24 bit addressing 11 16 bit addressing addr 19 9 Gen ID addr 7 PLL bypass setting 0 Bypass 1 Normal operation addr 6 5 PLL output divider set...

Page 154: ...Reload Count and Compare register A090 0030 Timer 2 Reload Count and Compare register A090 0034 Timer 3 Reload Count and Compare register A090 0038 Timer 4 Reload Count and Compare register A090 003C...

Page 155: ...r A090 00B0 Timer 8 Reload Step register A090 00B4 Timer 9 Reload Step register A090 00B8 Reserved A090 00BC Reserved A090 00C0 Reserved A090 00C4 Interrupt Vector Address Register Level 0 A090 00C8 I...

Page 156: ...Address Register Level 26 A090 0130 Interrupt Vector Address Register Level 27 A090 0134 Interrupt Vector Address Register Level 28 A090 0138 Interrupt Vector Address Register Level 29 A090 013C Inter...

Page 157: ...Memory Base A090 01D4 System Memory Chip Select 0 Dynamic Memory Mask A090 01D8 System Memory Chip Select 1 Dynamic Memory Base A090 01DC System Memory Chip Select 1 Dynamic Memory Mask A090 01E0 Syst...

Page 158: ...gisters control the AHB arbiter bandwidth allocation scheme A090 0214 External Interrupt 0 Control register A090 0218 External Interrupt 1 Control register A090 021C External Interrupt 2 Control regis...

Page 159: ...nel 9 Channel 10 Channel 11 BRC3 Channel 12 Channel 13 Channel 14 Channel 15 HMSTR 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Channel 0 4 8 or 12 Channel 1 5...

Page 160: ...2 register records AHB master and slave values present when any AHB error is found This register also records which error condition was triggered Note that this value is not reset on powerup but is re...

Page 161: ...ory The other fields in this register and the AHB Error Status 1 register are not valid if this bit is set D18 DE Not reset CPU data error An error was found on the CPU data access to external memory...

Page 162: ...eserved EIC Reserved SERDC Bits Access Mnemonic Reset Description D31 24 N A Reserved N A N A D23 R W EIC 0x0 AHB Error Interrupt Clear Write a 1 then a 0 to this register to clear the AHB error inter...

Page 163: ...LSE 0x0 Timer 8 low step enable 0 Low Step register disabled 1 Low Step register enabled D16 R W T8HSE 0x0 Timer 8 high step enable 0 High Step register disabled 1 High Step register enabled D15 R W T...

Page 164: ...0x0 Timer 7 enable 0 Timer reset 1 Timer enabled D06 R W T6E 0x0 Timer 6 enable 0 Timer reset 1 Timer enabled D05 R W T5E 0x0 Timer 5 enable 0 Timer reset 1 Timer enabled D04 R W T4E 0x0 Timer 4 enabl...

Page 165: ...mpare mode toggle output on match 010 Compare mode pulse output on match 011 Capture mode on input falling edge 100 Capture mode on input rising edge 101 Capture mode on every 2nd rising edge 110 Capt...

Page 166: ...ncy D03 R W Int Sel 0x0 Interrupt select 0 Interrupt disable 1 Generate IRQ D02 R W Up Down 0x0 Up Down select 0 Up counter 1 Down counter D01 R W Bit timer 0x0 32 or 16 bit timer 0 16 bit timer 1 32...

Page 167: ...10 Reserved 11 Quadrature decoder counter mode D15 R W TE 0x0 Timer enable 0 Timer disabled 1 Timer enabled D14 12 R W Cap Comp 0x0 Capture and compare mode functions Applicable only when in 16 bit t...

Page 168: ...rnal event 01 External low level gated timer 10 External high level gated timer 11 Concatenate the lower timer Note When either external gated option is selected the time clock select bits deter mine...

Page 169: ...to create a clock output 11 Reserved D15 R W TE 0x0 Timer enable 0 Timer disabled 1 Timer enabled D14 12 R W Cap Comp 0x0 Capture and compare mode functions Applicable only when in 16 bit timer mode 0...

Page 170: ...11 External event D05 04 R W Timer mode 1 0x0 Timer mode 1 00 Internal timer or external event 01 External low level gated timer 10 External high level gated timer 11 Concatenate the lower timer When...

Page 171: ...s 6 through 9 Register Register bit assignment 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 High High Bits Access Mnemonic Reset Description D31 00 R W High 0x...

Page 172: ...5 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Lo Step Dir Hi Step Dir Lo Step Hi Step Bits Access Mnemonic Reset Description D31 R W Hi Step Dir 0x0 High step direction 0 Subtract the high step...

Page 173: ...15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Rel Dir Reserved Rel Step Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 R W Rel Dir 0x0 Reload step direction 0 Subtract...

Page 174: ...upt is generated if enabled If configured for a 32 bit timer bits 31 16 timer reload D15 00 R W Rel 15 0 0x0 Timer Reload Bits 15 00 Count register This value is loaded into the Timer register after t...

Page 175: ...ograms each interrupt configuration for each priority level Individual register mapping This table shows how the 32 individual 8 byte registers are mapped in the eight 32 bit registers 13 12 11 10 9 8...

Page 176: ...hat the extra access is not optimized away A090 015C Int Config 24 Int Config 25 Int Config 26 Int Config 27 A090 0160 Int Config 28 Int Config 29 Int Config 30 Int Config 31 Register 31 24 23 16 15 0...

Page 177: ...W IS addr 0x0 Interrupt service routine address A read to this register updates the priority logic block and masks the current and any lower priority interrupt requests Write the value of the interru...

Page 178: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Interrupt status raw ISRAW Interrupt status raw ISRAW Bits Access Mnemonic Reset Description D31 00 R ISRAW 0x0 Int...

Page 179: ...set cannot be cleared D06 N A Reserved N A N A D05 R W SWWI 0x0 Software watchdog interrupt clear Write a 1 then a 0 to this register to clear the software watchdog interrupt D04 R W SWWIC 0x0 Softwar...

Page 180: ...4 23 22 21 20 19 18 17 16 30 Watchdog Timer Watchdog Timer Bits Access Mnemonic Reset Description D31 00 R W Watchdog timer 0x0 Watchdog timer A read to this register gives the current value of the wa...

Page 181: ...68 001 Divide by 2 74 9568 37 4784 010 Divide by 4 37 4784 18 7392 011 Divide by 8 18 7393 9 3693 100 Divide by 16 9 3693 4 6848 Software can write to the CSC bits to reduce the clock frequency of the...

Page 182: ...R W AES 0x0 AES 0 Clock disabled 1 Clock enabled D08 R W ADC 0x1 ADC 0 Clock disabled 1 Clock enabled D07 06 N A Reserved N A Always write to 00 D05 R W SPI 0x1 SPI 0 Clock disabled 1 Clock enabled D0...

Page 183: ...Description D31 29 R RST STAT Not reset Reset status 001 External reset using reset_n 010 External reset using sreset_n 011 PLL change reset 100 Software watchdog reset 101 AHB bus monitor reset Stat...

Page 184: ...Always write to 00 D05 R W SPI 0x1 SPI 0 Module reset 1 Module enabled D04 R W UART D 0x1 UART D 0 Module reset 1 Module enabled D03 R W UART C 0x1 UART C 0 Module reset 1 Module enabled D02 R W UART...

Page 185: ...04 03 R Boot width HW strap gpio_a 0 addr 23 If boot mode is set to boot from flash 00 8 bit 01 32 bit 10 32 bit 11 16 bit If boot mode is set to boot from SPI 00 Reserved 01 Boot using 8 bit address...

Page 186: ...NR 1 NF 1 ClkOut PLL Vco OD 1 Restrictions RefClk NR 1 range 275KHz 550MHz PLL Vco range 110MHz 550MHz Register Register bit assignment Bits Access Mnemonic Reset Description D31 17 N A Reserved N A...

Page 187: ...228 The power management register controls the processor power management features Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved INTI...

Page 188: ...U resumes and executes a CPU Wake Interrupt when activity is detected by one of the wakeup modules selected by the other bits in this register The PC will be restored to the address after the coproces...

Page 189: ...1 wakeup D16 R W Ext Int 0 0x0 External interrupt 0 interrupt wakeup 0 Do not wake on external 0 interrupt 1 Wake on external 0 wakeup D15 13 N A Reserved N A N A D12 R W RTC 0x0 RTC wakeup 0 Do not...

Page 190: ...not wake on character match 1 Wake on character match D00 R W Enet 0x0 Ethernet wakeup 0 Do not wake on Ethernet packet 1 Wake on Ethernet packet Bits Access Mnemonic Reset Description 13 12 11 10 9 8...

Page 191: ...mory chip select 1 with a minimum size of 4K The powerup default settings produce a memory range of 0x1000 0000 0x1FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18...

Page 192: ...y range of 0x2000 0000 0x2FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 1 base CS1B Reserved Chip select 1 base CS1B 13 12 11 10 9 8 7 6 5...

Page 193: ...range of 0x3000 0000 0x3FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 2 base CS2B Reserved Chip select 2 base CS2B 13 12 11 10 9 8 7 6 5 4...

Page 194: ...range of 0x4000 0000 0x4FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 3 base CS3B Reserved Chip select 3 base CS3B 13 12 11 10 9 8 7 6 5 4...

Page 195: ...ge of 0x5000 0000 0x5FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 0 base CS0B Reserved Chip select 0 base CS0B 13 12 11 10 9 8 7 6 5 4 3 2...

Page 196: ...nge of 0x6000 0000 0x6FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 1 base CS1B Reserved Chip select 1 base CS1B 13 12 11 10 9 8 7 6 5 4 3...

Page 197: ...nge of 0x7000 0000 0x7FFF FFFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 2 base CS2B Reserved Chip select 2 base CS2B 13 12 11 10 9 8 7 6 5 4 3...

Page 198: ...ip select 3 base CS3B Reserved Chip select 3 base CS3B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Chip select 3 mask CS3M Reserved Chip select 3 mask CS3M CS...

Page 199: ...31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved GENID Reserved Bits Access Mnemonic Reset Description D31 11 N A Reserved N A N A D10 00 R GENID HW strap addr 19 09 General Purpose ID regist...

Page 200: ...erted before sending to the interrupt controller If edge sensitive generate an interrupt on the falling edge of the external interrupt D00 R W LVEDG 0x0 Level edge 0 Level sensitive interrupt 1 Edge s...

Page 201: ...C standby mode Allows the RTC module to be placed in low power mode 0 The RTC module is placed in standby mode and cannot be accessed by the CPU The RTC clock must be enabled when in standby mode bit...

Page 202: ...S Y S T E M C O N T RO L M OD U L E RTC Module Control register 202 Hardware Reference NS9215...

Page 203: ...ower SDRAM Asynchronous static memory device support including RAM ROM and Flash with and without asynchronous page mode Can operate with cached processors with copyback caches Can operate with uncach...

Page 204: ...rovides two features to enable this Dynamic memory refresh over soft reset A mechanism to place the dynamic memories into self refresh mode Self refresh mode can be entered as follows 1 Set the SREFRE...

Page 205: ...cess memory chip select 1 Clearing the address mirror bit M in the Control register disables address mirroring and memory chip select 0 chip select 4 and memory chip select 1 can be accessed as normal...

Page 206: ...mory controller to configure chip select 0 6 The address mirroring is disabled by clearing the address mirror M field in the Control register 7 The ARM reset and interrupt vectors are copied from flas...

Page 207: ...ifferent types of memory devices See StaticMemory Configuration 0 3 registers on page 251 for more information Device Write protect Page mode Buffer ROM Enabled Disabled Disabled a Page mode ROM Enabl...

Page 208: ...Wait Delay register StaticWaitWr These registers allow transfers with up to 32 wait states If a very slow static memory device has to be accessed however you can enable the static configuration exten...

Page 209: ...that the transfer initiated from the current main bus master the internal bus transfer takes several external bus transfers to complete For example if bank 0 is configured as 8 bit wide memory and a...

Page 210: ...tic memory read controls Output enable programmable delay ROM SRAM and flash Asynchronous page mode read Output enable programmable delay The delay between the assertion of the chip select and the out...

Page 211: ...when accessing the external device with load multiple LDM or store multiple STM CPU instructions External memory read transfer with two wait states This diagram shows an external memory read transfer...

Page 212: ...ernal memory read transfers with zero wait states This diagram shows external memory read transfers with zero wait states WAITRD 0 These transfers can be non sequential transfers or sequential transfe...

Page 213: ...ed The first read requires five arbitration cycles the three subsequent sequential reads have zero AHB cycles added because the external transfers are automatically generated Burst of two wait states...

Page 214: ...lower two address bits change between subsequent accesses At the end of the burst the chip select and output enable lines are deasserted together As y n c h ronous page mode rea d Tim ing and p ara me...

Page 215: ...A total of eight AHB wait states are added during this transfer five AHB arbitration cycles and then one for each of the subsequent reads WAITRD and WAITPAGE are 0 Timing parameter Value WAITRD 2 WAIT...

Page 216: ...e the byte lane selects instead of the write enables SRAM Write timing for SRAM starts with assertion of the appropriate memory bank chip selects cs n _n and address signals addr 27 0 _n The write acc...

Page 217: ...s added External memory write transfer with two write enable delay states This diagram shows a single external memory write transfer with two write enable delay states WAITWEN 2 One wait state is adde...

Page 218: ...equential or nonsequential to sequential with any value of HBURST The maximum speed of write transfers is controlled by the external timing of the write enable relative to the chip select so all exter...

Page 219: ...rent memory banks Read to write same memory bank Read to write different memory banks B u s t u r n a r o u n d T i m i n g a n d p a r a m e t e r s This section shows bus turnaround timing diagrams...

Page 220: ...ait states to allow the previous write access to complete and the three standard wait states for the read transfer Read followed by a write with two turnaround cycles TIs diagram shows a zero wait rea...

Page 221: ...Any access tried with a size greater that a word causes an error response Each memory chip select can be 8 16 or 32 bits wide The memory type used determines how the st_we_n and data_mask signals are...

Page 222: ...t memory The st_we_n signal from the memory controller is not used For write transfers the appropriate data_mask 3 0 byte lane signals are asserted low and direct the data to the addressed bytes For r...

Page 223: ...e the next two figures Memory banks constructed from 16 bit memory Memory bank constructed from 32 bit memory The next figure shows connections for a typical memory system with different data width me...

Page 224: ...RAM 128Kx8 SRAM A 15 0 CE_n OE_n WE_n UB_n LB_n IO 15 0 A 15 0 CE_n OE_n WE_n UB_n LB_n IO 15 0 A 16 0 CE_n OE_n WE_n IO 7 0 A 16 0 CE_n OE_n WE_n IO 7 0 A 16 0 CE_n OE_n WE_n IO 7 0 A 16 0 CE_n OE_n...

Page 225: ...words into one 32 bit word and places the result onto the AHB bus Word transfers are the widest transfers supported by the memory controller Any access tried with a size larger than a word generates a...

Page 226: ...hift value All other address bits must be set to 0 12 Set the SDRAMInit value in the Dynamic Control register to 00 Issue SDRAM nor mal operation command 13 Enable the buffers by writing a 1 to the bu...

Page 227: ...r left shift Device size Configuration Load Mode register left shift 16M 2 x 1M x 16 10 4 x 2M x 8 11 64M 1 x 2M x 32 10 2 x 4M x 16 10 4 x 8M x 8 11 128M 1 x 4M x 32 10 2 x 8M x 16 11 4 x 16M x 8 12...

Page 228: ...data 31 16 on the processor 32 bit wide configuration Device size Configuration Load Mode register left shift 16M 1 x 1M x 16 9 2 x 2M x 8 10 64M 1 x 4M x 16 9 2 x 8M x 8 10 128 1 x 8M x 16 10 2 x 16M...

Page 229: ...figurations Signal 16M device SDRAM signal 64M device SDRAM signal 128M device SDRAM signal 256M device SDRAM signal 512M device SDRAM signal Signal 16M device SDRAM signal 64M device SDRAM signal 128...

Page 230: ...512M device SDRAM signal Address Register Description A070 0000 Control register Control register A070 0004 Status register Status register A070 0008 Config register Configuration register A070 0020 D...

Page 231: ...nfig2 Dynamic Memory Configuration Register 2 A070 0144 DynamicRasCas2 Dynamic Memory RAS and CAS Delay 2 A070 0160 DynamicConfig3 Dynamic Memory Configuration Register 3 A070 0164 DynamicRasCas3 Dyna...

Page 232: ...aticWaitRd2 Static Memory Read Delay 2 A070 0250 StaticWaitPage2 Static Memory Page Mode Read Delay 2 A070 0254 StaticWaitWr2 Static Memory Write Delay 2 A070 0258 StaticWaitTurn2 Static Memory Turn R...

Page 233: ...abled state D01 R W ADDM Address mirror 0 Normal memory map 1 Reset memory map Static memory chip select 1 is mirrored onto chip select 0 and chip select 4 reset value on reset_n Indicates normal or r...

Page 234: ...14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved SA WBS Bits Access Mnemonic Description D31 03 N A Reserved N A do not modify D02 R SA Self refresh acknowledge SREFACK 0 Normal m...

Page 235: ...iption D31 01 N A Reserved N A do not modify D00 R W END Endian mode 0 Little endian mode 1 Big endian mode The value of the endian bit on power on reset reset_n is determined by the gpio_a 3 signal T...

Page 236: ...ify D02 R W SR Self refresh request SREFREQ 0 Normal mode 1 Enter self refresh mode reset value on reset_n By writing 1 to this bit self refresh can be entered under software control Writing 0 to this...

Page 237: ...enly distributed There might be slight variations however when the auto refresh command is issued depending on the status of the memory controller D y n a m ic Me m o ry R e a d C o n f i g u r a t i...

Page 238: ...d for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 R...

Page 239: ...mally is found in SDRAM datasheets as tRAS Note The Dynamic Memory Active to Precharge Command Period register is used for all four dynamic memory chip selects The worst case value for all chip select...

Page 240: ...c M e m o r y L a s t D a t a O u t t o A c t i v e T i m e r e g i s t e r Address A070 003C The Dynamic Memory Last Data Out to Active Time register allows you to program the last data out to active...

Page 241: ...idle then enter low power or disabled mode This value normally is found in SDRAM data sheets as tDAL or tAPW Note The Dynamic Memory Data in Active Command Time register is used for all four dynamic...

Page 242: ...L tRWL or tRDL Note The Dynamic Memory Write Recovery Time register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register Register bit...

Page 243: ...worst case value for all chip selects must be programmed Register Register bit assignment D y n a m ic Me m o ry A u t o R e f r e s h P e ri o d r e g i s t e r Address A070 004C The Dynamic Memory...

Page 244: ...d during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in S...

Page 245: ...controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as tRRD Note The Dynamic Memory Active Bank A to Active Bank B Time register is used for all f...

Page 246: ...ed mode This value normally is found in SDRAM datasheets as tMRD or tRSA Note The Dynamic Memory Load Mode register to Active Command Time register is used for all four chip selects The worst case val...

Page 247: ...ic Memory Configuration register It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions If necessary however these contr...

Page 248: ...otected D19 R W BDMC Buffer enable 0 Buffer disabled for accesses to this chip select reset value on reset_n 1 Buffer enabled for accesses to this chip select The buffers must be disabled during SDRAM...

Page 249: ...ess mapping bank row column 0 1 000 00 16 Mb 2Mx8 2 banks row length 11 column length 9 0 1 000 01 16 Mb 1Mx16 2 banks row length 11 column length 8 0 1 001 00 64 Mb 8Mx8 4 banks row length 12 column...

Page 250: ...row column 1 1 000 00 16 Mb 2Mx8 2 banks row length 11 column length 9 1 1 000 01 16 Mb 1Mx16 2 banks row length 11 column length 8 1 1 001 00 64 Mb 8Mx8 4 banks row length 12 column length 9 1 1 001...

Page 251: ...3 registers configure the static memory configuration It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait unt...

Page 252: ...other than SRAM is attached to the static ram chip select D18 09 N A Reserved N A do not modify D08 R W EW Extended wait 0 Extended wait disabled reset value on reset_n 1 Extended wait enabled Extend...

Page 253: ...case for reads all byte_lane 3 0 bits must be high which means that the byte lane state bit must be low 16 bit wide static memory devices usually have the byte_lane 3 0 signals connected to the nUB an...

Page 254: ...current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode Register D02 R W BMODE Burst mode Allows the static output enable signal to toggle du...

Page 255: ...re are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode Register Register bit assignment Bits Access Mnemonic Description D31 04 N...

Page 256: ...0230 0250 0270 The Static Memory Page Mode Read Delay 0 3 registers allow you to program the delay for asynchronous page mode sequential accesses These registers control the overall period for the re...

Page 257: ...on or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode These registers are not used if the extended wait bit is enab...

Page 258: ...ons Wait until the memory controller is idle then enter low power or disabled mode Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved WTWR...

Page 259: ...cles added between static memory read and write accesses The WAITTURN field also controls the number of turnaround cycles between static memory and dynamic memory accesses Bits Access Mnemonic Descrip...

Page 260: ...M E MO R Y C O N T ROL L E R StaticMemory Turn Round Delay 0 3 registers 260 Hardware Reference NS9215...

Page 261: ...t end module provides all of the control functions to the MAC Features The Ethernet MAC module provides the following Station address logic SAL Statistics module Interface to MII Media Independent Int...

Page 262: ...ions module E t h e r n e t M A C The Ethernet MAC includes a full function 10 100 Mbps Media Access Controller MAC station address filtering logic SAL statistic collection module STAT and MII Etherne...

Page 263: ...ess Controller Performs the CSMA CD function MCS MAC control sublayer TFUN Transmit function RFUN Receive function HOST Host interface Provides an interface for control and configuration CLK Reset Clo...

Page 264: ...ming frames and filters the frames before they are stored in the Ethernet front end SAL Station address logic Performs destination address filtering MII Media Independent Interface Provides the interf...

Page 265: ...sses the 64 bit multicast hash table created in the HT1 and HT2 registers See Sample hash table code on page 334 If the current receive frame is a multicast frame and the 6 bit CRC addresses a bit in...

Page 266: ...alid checksum and size from the Ethernet MAC and commits them to external system memory Bad frames for example invalid checksum or code violation and frames with unacceptable destination addresses are...

Page 267: ...e receive size of the frame are stored in a separate 32 entry receive status FIFO the RX_RD logic is notified that a good frame is in the FIFO If the RX_WR logic tries to write to a full receive data...

Page 268: ...er descriptor are skipped The search stops as soon as the logic encounters an available buffer that is large enough to hold the entire receive frame The pointers to the first buffer descriptor in each...

Page 269: ...e the ENABLE bit from 0 to 1 and reinitialize the buffer descriptors pointed to by the Buffer Descriptor Pointer register 1 Set the ERXINIT bit in the Ethernet General Control Register 1 7 Wait for RX...

Page 270: ...buffer descriptor RAM The next buffer descriptor is found using the initial buffer descriptor pointer in the TX Buffer Descriptor Pointer register TXPTR When the WRAP bit is not set the next buffer d...

Page 271: ...ic clears this bit after emptying a buffer The system software sets this bit as required to signal that the buffer is ready for transmission If the TX_WR logic detects that this bit is not set when th...

Page 272: ...riptor in a frame has a non zero value The TX_WR logic stops processing frames until TCLER clear transmit logic in Ethernet General Control Register 2 is toggled from low to high to resume processing...

Page 273: ...the address is not aligned on a 32 bit boundary and the misaligned bus address response mode is set in the Miscellaneous System Configuration register In addition accesses to non existent addresses r...

Page 274: ...overflow One of the statistics counters has overflowed Individual counters can be masked using the CAM1 and CAM2 registers TX Transmit buffer closed I bit set in Transmit buffer descriptor and buffer...

Page 275: ...lticast address filtering example 1 To accept only multicast packets with destination address 0x01_00_5E_00_00_00 using entry 0 the registers are set as shown RPETFUN MAC1 1 0 MAC TX logic MIIM MII Ma...

Page 276: ...a large amount of gates Therefore the logic is designed such that only the MFILTEN register bits are synchronized and when these bits are cleared changes in the other register values are not seen at...

Page 277: ...ket Gap register A060 040C IPGR Non Back to Back Inter Packet Gap register A060 0410 CLRT Collision Window Retry register A060 0414 MAXF Maximum Frame register A060 0418 A060 041C Reserved A060 0420 M...

Page 278: ...ter 0 A060 0A44 MFILTL1 Multicast Low Address Filter Register 1 A060 0A48 MFILTL2 Multicast Low Address Filter Register 2 A060 0A4C MFILTL3 Multicast Low Address Filter Register 3 A060 0A50 MFILTL4 Mu...

Page 279: ...MFMSKH2 Multicast High Address Mask Register 2 A060 0AAC MFMSKH3 Multicast High Address Mask Register 3 A060 0AB0 MFMSKH4 Multicast High Address Mask Register 4 A060 0AB4 MFMSKH5 Multicast High Addres...

Page 280: ...allow the RX_RD logic to request the AHB bus to DMA receive frames into system memory Set this bit to zero to temporarily stall the receive side Ethernet DMA The RX_RD logic stalls on frame boundaries...

Page 281: ...er pointer descriptor are programmed into the transmit packet processor D21 R W Not used 1 Always write as 1 D20 R W Not used 0 Always write as 0 D19 R W ERXINIT 0 Enable initialization of RX buffer d...

Page 282: ...c to guarantee that all functions get reset D08 R W ITXA 0 Insert transmit source address 0 Source address for Ethernet transmit frame taken from data in TX_FIFO 1 Insert the MAC Ethernet source addre...

Page 283: ...transmit packet processor D06 04 R W Not used 0 Always write as 0 D03 R W TKICK 0 Transmit DMA state machine enable 0 1 transition used by software to start a DMA transfer after a buffer descriptor ha...

Page 284: ...last transmit buffer descriptor for the frame Register Reserved 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved RX INIT Reserved Bits Access Mnemonic Res...

Page 285: ...ing frames and sets the TXERR bit in the Ethernet Interrupt Status register D11 R TXAED 0x0 TX abort excessive deferral When set indicates that the frame was deferred in excess of 6071 nibble times in...

Page 286: ...x000 If the HUGE bit is set to 0 the frame is truncated If TXAJ is set the TX_WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register D07 R Not used 0x0 Alway...

Page 287: ...empt being made was found at some point since the last receive statistics A carrier event results when the interface signals to the PHY have the following values MRXER 1 MRXDV 0 RXD 0xE The event is b...

Page 288: ...12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved SRST Not used RPER FUN RPE MCST RPET FUN Reserved LOOP BK RXEN Not used Not used Bits Access Mnemonic Reset...

Page 289: ...eceive frames Bits Access Mnemonic Reset Description Reserved 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Rsvd EDE FER LONGP PUREP CRCEN Not used HUG...

Page 290: ...r transmit frames below D06 R W VLANP 0 VLAN pad enable Set to 1 to have the MAC pad all short transmit frames to 64 bytes and to append a valid CRC This bit is used in conjunction with auto detect pa...

Page 291: ...as 0 D00 R W FULLD 0 Full duplex 0 The MAC operates in half duplex mode 1 The MAC operates in full duplex mode Bits Access Mnemonic Reset Definition Type AUTOP VLANP PADEN Action Any X X 0 No pad che...

Page 292: ...ffset of the minimum period between the end of any transmitted frame to the beginning of the next frame Full duplex mode Register value should be the appropriate period in nibble times minus 3 Recomme...

Page 293: ...uring the timing of IPGR1 the MAC defers to carrier If carrier comes after IPGR1 the MAC continues timing IPGR2 and transmits knowingly causing a collision This ensures fair access to the medium IPGR1...

Page 294: ...nfigured networks Because the collision window starts at the beginning of transmissions the preamble and SFD start of frame delimiter are included The default value 0x37 55d corresponds to the frame b...

Page 295: ...frame adds four octets for a total of 1522 octets To use a shorter maximum length restriction program this field accordingly Note If a proprietary header is allowed this field should be adjusted acco...

Page 296: ...s used as the input to the clock divide logic See the Clocks field settings table for settings that can be used with AHB clock hclk frequencies D01 R W SPRE 0 Suppress preamble 0 Causes normal cycles...

Page 297: ...scan for read data Set to 1 to have the MII Management module perform read cycles continuously This is useful for monitoring link fail for example Note SCAN must transition from a 0 to a 1 to initiate...

Page 298: ...an be addressed D07 05 N A Reserved N A N A D04 00 R W RADR 0x00 MII PHY register address Represents the 5 bit PHY register address field for management cycles Up to 32 registers within a single PHY d...

Page 299: ...read data Read data is obtained by reading from this register after an MII Management read cycle An MII Management read cycle is executed by loading the MII Management Address register then setting t...

Page 300: ...ta is not yet valid Also indicates that SCAN READ is not valid for automatic scan reads D01 R SCAN 0 Automatically scan for read data in progress When set to 1 indicates that continuous MII Management...

Page 301: ...example the station address logic can be programmed to accept all multicast frames all broadcast frames and frames to the programmed destination address Reserved OCTET5 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 302: ...the receive frame will be accepted otherwise the receive frame is rejected HT1 stores enables for the lower 32 CRC addresses HT2 stores enables for the upper 32 CRC addresses HT1 Address A060 0504 Re...

Page 303: ...ad frame transmitted and received that falls within the specified frame length limits of the counter for example TR127 counts 65 127 byte frames The frame length excludes framing bits and includes the...

Page 304: ...s R W A060_069C RBYT Receive byte counter R W A060_06A0 RPKT Receive packet counter R W A060_06A4 RFCS Receive FCS error counter R W A060_06A8 RMCA Receive multicast packet counter R W A060_06AC RBCA...

Page 305: ...reater than 1518 bytes non VLAN or 1522 bytes VLAN excluding multicast frames This counter does not look at range length errors Receive control frame packet counter A060 06B0 Incremented for each MAC...

Page 306: ...ceived that is less than 64 bytes in length contains a valid FCS and is otherwise well formed This counter does not look at range length errors Receive oversize packet counter A060 06D0 Incremented ea...

Page 307: ...6E4 TPKT Transmit packet counter R W A060_06E8 TMCA Transmit multicast packet counter R W A060_06EC TBCA Transmit broadcast packet counter R W A060_06F0 Reserved N A N A A060_06F4 TDFR Transmit deferr...

Page 308: ...mented for each frame that was deferred on its first transmission attempt This counter does not include frames involved in collisions Transmit excessive deferral packet counter A060 06F8 Incremented f...

Page 309: ...field of the Collision Window Retry register and was aborted Transmit total collision packet counter A060 070C Incremented by the number of collisions experienced during the transmission of a frame No...

Page 310: ...gister 1 CAR1 and Carry Register 2 CAR2 have carry bits for all of the statistics counters These carry bits are set when the associated counter reaches a rollover condition These carry bits also can c...

Page 311: ...ry bit D25 R C C1MGV 0 Carry register 1 TRMGV counter carry bit D24 17 N A Reserved N A N A D16 R C C1RBY 0 Carry register 1 RBYT counter carry bit D15 R C C1RPK 0 Carry register 1 RPKT counter carry...

Page 312: ...OV 0 Carry register 2 TOVR counter carry bit D15 R C C2TUN 0 Carry register 2 TUND counter carry bit D14 R C C2TFG 0 Carry register 2 TFRG counter carry bit D13 R C C2TBY 0 Carry register 2 TBYT count...

Page 313: ...RMGV counter carry bit mask D24 17 N A Reserved N A N A D16 R W M1RBY 1 Mask register 1 RBYT counter carry bit mask D15 R W M1RPK 1 Mask register 1 RPKT counter carry bit mask D14 R W M1RFC 1 Mask reg...

Page 314: ...ounter carry bit mask D15 R W M2TUN 1 Mask register 2 TUND counter carry bit mask D14 R W M2TFG 1 Mask register 2 TFRG counter carry bit mask D13 R W M2TBY 1 Mask register 2 TBYT counter carry bit mas...

Page 315: ...TR 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 RXAPTR Bits Access Mnemonic Reset Description D31 00 R W RXAPTR 0x00000000 RX_A Buffer Descriptor Pointer Conta...

Page 316: ...CPTR 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 RXCPTR Bits Access Mnemonic Reset Description D31 00 R W RXCPTR 0x00000000 RX_C Buffer Descriptor Pointer Con...

Page 317: ...at the same time the interrupt bit is being cleared the interrupt status bit remains set and the interrupt signal remains set Note For diagnostics software can cause any of these interrupt status bit...

Page 318: ...frame because all four buffer rings are disabled or full D16 R C RXBR 0 Assigned to RX interrupt New frame available in the RX_FIFO This bit is used for diagnostics D15 07 N A Reserved N A N A D06 R C...

Page 319: ...rrupt Status register on page 317 for information about restarting the transmitter when this bit is set Bits Access Mnemonic Reset Description Reserved 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 2...

Page 320: ...N_TXDONE 0 Enable the TXDONE interrupt bit D01 R W EN_TXERR 0 Enable the TXERR interrupt bit D00 R W EN_TXIDLE 0 Enable the TXIDLE interrupt bit Bits Access Mnemonic Reset Description Reserved TXPTR 1...

Page 321: ...Reserved Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W TXRPTR 0x00 Contains a pointer to a buffer descriptor in the TX buffer descriptor RAM Note This pointer is the 8...

Page 322: ...is loaded by the TX_WR logic when a transmit frame is aborted by the MAC or when the MAC finds a CRC error in a frame TXERBD also is loaded if a buffer descriptor that is not the first buffer descrip...

Page 323: ...egister Note This pointer is the 8 bit physical address of the TX buffer descriptor RAM and points to the first location of the four location buffer descriptor The byte offset of this buffer descripto...

Page 324: ...erved RXBOFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Bits Access Mnemonic Reset Description D31 11 N A Reserved N A N A D10 00 R RXBOFF 0x000 Con...

Page 325: ...et from the start of the pool C ring The offset is updated at the end of the RX packet and will have the offset to the next buffer descriptor that will be used RXCOFF can be used to determine where th...

Page 326: ...10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Bits Access Mnemonic Reset Description D31 10 N A Reserved N A N A D09 00 R TXOFF 0x000 Contains a 10 bit byte off...

Page 327: ...zation scheme used for these registers see Clock synchronization on page 276 Multicast Low Address Filter Register 0 Address A060 0A40 Multicast Low Address Filter Register 1 Address A060 0A44 Multica...

Page 328: ...ilter Register 4 Address A060 0A70 Multicast High Address Filter Register 5 Address A060 0A74 D31 00 R W Default 0x0000 0000 MFILTL6 D31 00 R W Default 0x0000 0000 MFILTL7 D31 16 R Default 0x0000 0000...

Page 329: ...et to 1 in the mask to enable or include that bit in the address filter Bits are set to 0 in the mask if they are not included or are disabled in the address filter These bits become don t cares For a...

Page 330: ...er 2 Address A060 0AA8 Multicast High Address Mask Register 3 Address A060 0AAC Multicast High Address Mask Register 4 Address A060 0AB0 D31 00 R W Default 0x0000 0000 MFMSKL4 D31 00 R W Default 0x000...

Page 331: ...he eight entries in the multicast address filter logic For an explanation of the synchronization scheme used for this register see Clock synchronization on page 276 Register D15 00 R W Default 0x0000...

Page 332: ...Disable entry 1 Enable entry D06 R W MFILTEN6 0x0000 0000 Enable entry 6 of multicast address filter 0 Disable entry 1 Enable entry D05 R W MFILTEN5 0x0000 0000 Enable entry 5 of multicast address fil...

Page 333: ...bit in the Ethernet General Control Register 1 This bit must be cleared before enabling the Ethernet receiver Register Register bit assignment D31 11 R W Not used D10 00 R W Buffer length D31 00 R W D...

Page 334: ...its 28 23 of the Ethernet destination address CRC The polynomial is the same as that used for the Ethernet FCS G x x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x 1 static ETH_ADDRESS mc...

Page 335: ...the MAC addresses setup by set_hash_bit The CRC value of each MAC address is calculated and the lower six bits are used to generate a value between 0 and 64 The corresponding bit in the 64 bit hash t...

Page 336: ...inter to hash table bit position of bit to set Return Values none static void set_hash_bit BYTE table int bit int byte_index bit_index byte index bit 3 bit_index bit 7 table byte_index 1 bit_index Fun...

Page 337: ...index BYTE lsb WORD16 copy_mca 3 memcpy copy_mca mca sizeof copy_mca for index 0 index 3 index copy_mca index SWAP16 copy_mca index mcap copy_mca crc 0xffffffffL for mca_word 0 mca_word 3 mca_word bp...

Page 338: ...T C O M M U N I C A T I O N M O D UL E Sample hash table code 338 Hardware Reference NS9215 bp rotate bp RIGHT 1 CRC calculation done The 6 bit result resides in bit locations 28 23 result crc 23 0x3f...

Page 339: ...tion address These two steps are repeated until the DMA transfer is complete Note Optimal performance is achieved when both the source address and destination address are aligned Initiating DMA transf...

Page 340: ...descriptors Important A DMA channel configured for more than the maximum number of buffer descriptors operates in an unpredictable fashion DMA buffer descriptor diagram Field descriptions follow Sourc...

Page 341: ...essage frame The DMA controller uses this bit to assert the normal channel completion status when the byte count reaches zero Full F bit The Full F bit when set indicates that the buffer descriptor is...

Page 342: ...all accesses on the selected peripheral chip select If configuration registers or memory also need to be accessed you can use high level address bits and an external gate to disable the PDEN signal Y...

Page 343: ...pheral The CLK signal shown is for reference and its frequency is equal to the speed grade of the part For peripheral writes the PDEN signal is an AND function of the active status of st_cs_n n and we...

Page 344: ...processor treats the REQ and DONE signals as asynchronous level signals REQ signal The external peripheral can initiate a DMA transfer at any time by asserting the REQ signal The external peripheral...

Page 345: ...res the REQ and DONE signals For memory to peripheral transfers the DMA control logic ignores the DONE signal S t a ti c R AM c hi p s e l e c t c o n f i g u r a ti o n The AHB DMA controller accesse...

Page 346: ...ations this field can be set to 0 Write Enable Delay WWEN User defined For most applications this field can be left in the default state Write Delay WTWR User defined For most applications this field...

Page 347: ...tion The external DMA module has two of these registers Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 BuffDesc BuffDesc Bit s Access Mnemonic Reset Des...

Page 348: ...y transfers The dma_req and dma_done signals are not used during memory to memory transfers D28 27 R W SW 0 Source width Defines the data bus width of the device attached to the source address specifi...

Page 349: ...y address 0 Increment source address pointer 1 Do not increment source address pointer D19 R W DINC_N 0 Destination address increment Controls whether the destination address pointers are incremented...

Page 350: ...reset state The reset field is written with the value specified on signals HWDATA 9 0 This field always reads back a 0 Note Writing a 1 to this field while the DMA channel is operational will have unp...

Page 351: ...fer not ready interrupt pending Set when the DMA channel encounters a buffer descriptor whose F bit is in the incorrect state The F bit must be set in order for the fetched buffer descriptor to be con...

Page 352: ...ble CAIP interrupt generation This interrupt should always be enabled during normal operation D20 R W PCIE 0 Enable PCIP interrupt generation D19 R WRAP 0 Read only debug field that indicates the last...

Page 353: ...s Access Mnemonic Reset Definition D31 02 R W Not used 0 This field must always be set to 0 D01 00 R W SEL 0 Chip select Defines which of the four memory interface chip select signals nmpmcstcsout n...

Page 354: ...E X T E R N A L D M A DMA Peripheral Chip Select register 354 Hardware Reference NS9215...

Page 355: ...on Standard AES Features Processes 32 bits at a time Is programmable for 128 192 or 256 bit key lengths Supports ECB CBC OFB CTR and CCM cipher modes Implements a hardware key expander to minimize sof...

Page 356: ...r d e s c r i p t o r The AES DMA buffer descriptor is the same as the external DMA buffer descriptor with the exception of the control bits AES op and AES control Ch 1 Ext DMA Source Key Expander FIF...

Page 357: ...ination buffer length The destination buffer length indicates the number of bytes to be written to the destination This field should be identical to the source buffer length for all modes with the exc...

Page 358: ...riptor Interrupt I bit The Interrupt bit when set tells the DMA controller to issue an interrupt to the CPU when the buffer is closed due to a normal channel completion The interrupt occurs regardless...

Page 359: ...bit key K0 K1 K2 K3 is expanded to the following 32 bit word sequence K0 K1 K40 K41 K42 K43 To expand the key backwards the hardware key expander needs K40 K43 A 192 bit key K0 K1 K2 K3 K5 K6 is expan...

Page 360: ...riptor sequence Key IV Data Processing flow diagram This is the buffer descriptor processing flow for CBC CFB OFB and CTR C C M m o d e CCM mode does not require an initialization vector Key Buffer Da...

Page 361: ...the AES module twice in CCM mode for both encryption and decryption modes Nonce buffer This is the format of the Nonce buffer Processing flow This is the CCM buffer descriptor processing flow Bits 12...

Page 362: ...A E S D AT A E N C R Y P T I O N D E C R Y P T I O N M O D U L E CCM mode 362 Hardware Reference NS9215...

Page 363: ...d ports include four UART ports one SPI port one I2 C port 2 multi function controlled ports and one analog to digital A D port UART channel C can be configured for HDLC operation The SPI UART and A D...

Page 364: ...eed peripherals Each channel has a transmit channel and a receive channel Servicing RX and FIFOs The DMA controller services the RX and FIFOs in a round robin manner When one of the FIFOs needs servic...

Page 365: ...eripheral has the ability to close the buffer early Control 15 W The Wrap W bit when set tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors The...

Page 366: ...The CPU must clear the F bit after all data has been read from the buffer If the DMA controller ever finds that this bit is not clear when the buffer descriptor is read the NRIP bit is set in the Int...

Page 367: ...escriptor and buffer data from system memory using the AHB master The DMA controller follows this process 1 Reads the first buffer descriptor as pointed to by the TX buffer descriptor pointer and INDE...

Page 368: ...ts The DMA direct mode and interrupt control register formats are the same for these modules The base address for the registers is 0x9000_0000 Write buffering in the MMU must be disabled for all regis...

Page 369: ...ter 0x9001_0020 UART A DMA TX Interrupt Configuration register 0x9001_0024 Reserved 0x9001_0028 UART A Direct Mode TX Data FIFO 0x9001_002C UART A Direct Mode TX Data Last FIFO 0x9001_0030 0x9001_0FFF...

Page 370: ...uffer Descriptor Pointer 0x9002_0020 UART C DMA TX Interrupt Configuration register 0x9002_0024 Reserved 0x9002_0028 UART C Direct Mode TX Data FIFO 0x9002_002C UAT C Direct Mode TX Data Last FIFO 0x9...

Page 371: ...A RX Control 0x9003_0008 SPI DMA RX Buffer Descriptor Pointer 0x9003_000C SPI DMA RX Interrupt Configuration register 0x9003_0010 SPI Direct Mode RX Status FIFO 0x9003_0014 SPI Direct Mode RX Data FIF...

Page 372: ...eral interrupts and to clear the interrupt bit Note An access type of R W means that the processor must write 1 to clear the value if the read value is 1 If the read value is 0 the write value must be...

Page 373: ...ding RX Set when the DMA channel finds either a bad buffer descriptor or a bad data buffer pointer The DMA channel remains in the ERROR state until the CE bit in the DMA Control register is cleared an...

Page 374: ...bit in the DMA Control register is cleared and then set again The DMA channel then uses the buffer descriptor as set in the index control field D22 R W TXNRIP 0x0 Buffer not ready interrupt pending T...

Page 375: ...ocessors The CPU must not access the Module Direct Mode RX Data FIFO Read register when this bit is set If this bit is set the read generates a bus error D14 R RX FIFO full 0x0 Receive status and data...

Page 376: ...I O DIRECT Reserved STATE Bit s Access Mnemonic Reset Description D31 R W CE 0x0 Channel enable 0 Disable DMA operation 1 Enable DMA operation D30 R W CA 0x0 Channel abort When set causes the current...

Page 377: ...ent 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 RXBDP RXBDP Bit s Access Mnemonic Reset Description D31 00 R W RXBDP 0x0 The first buffer descriptor in the ri...

Page 378: ...terrupt D24 R W RXNCIE 0x0 Enable the RXNCIP interrupt D23 R W RXECIE 0x0 Enable the RXECIP interrupt D22 R W RXNRIE 0x0 Enable the RXNRIP interrupt D21 R W RXCAIE 0x0 Enable the RXCAIP interrupt D20...

Page 379: ...ne the valid number of bytes in the 32 bit access The data is packed in little endian format Register Register bit assignment Bit s Access Mnemonic Reset Description D31 12 N A Reserved N A N A D11 09...

Page 380: ...0 Channel abort When set causes the current DMA operation to complete and closes the buffer The DMA channel remains idle until this bit is cleared D29 R W FLEX I O 0x0 0 DMA controlled by CPU 1 DMA co...

Page 381: ..._0020 9002_8020 9003_0020 The TX Interrupt Configuration register allows system software to configure the interrupt from the I O hub module transmit channel Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15...

Page 382: ...e the TXFUFIP interrupt D25 R W TXFSRIE 0x0 Enable the TXFSRIP interrupt D24 R W TXNCIE 0x0 Enable the NCIP interrupt D23 R W TXECIE 0x0 Enable the ECIP interrupt D22 R W TXNRIE 0x0 Enable the NRIP in...

Page 383: ...er is used when in direct mode of operation to write to the TX data FIFO and to cause a last status flag to be set for use by the peripheral The write can be 8 16 or 32 bit Register Register bit assig...

Page 384: ...I O HU B M OD UL E Module Direct Mode TX Data Last FIFO 384 Hardware Reference NS9215 31 March 2008...

Page 385: ...ve and transmit programmable bit rate generators High speed data transfer up to 1 8432 Mbps Programmable data format 5 to 8 data bits Odd even or no parity 1 or 2 stop bits MSB or LSB first Programmab...

Page 386: ...this table can be left at reset value Receive FIFO Interface Transmit FIFO Interface UART be 1 0 data 31 0 read write be 1 0 data 31 0 status 6 0 AHBBus ref_clk valid int RI DSR DCD RTS DTR CTS TXD R...

Page 387: ...input on GPIO_A 3 Baud rates This table shows the baud rates achieved with CLKref set to 29 4912 UART Interrupt Enable register 0x104 ETBEI 0x1 Enable the Transmitter Holding Register Empty Interrupt...

Page 388: ...s the state of the transmitter which allows character based flow control to achieve the same response time as hardware based flow control Example configuration Configure the character based flow contr...

Page 389: ...dback If you do want to collect feedback these are your options Poll the ENABLE field in the Force Transmit Character Control register until it reads 0 Poll the FORCE field in the Interrupt Status reg...

Page 390: ...9001_1008 Interrupt Status 9001_100C Receive Character GAP Control 9001_1010 Receive Buffer GAP Control 9001_1014 Receive Character Match Control 0 9001_1018 Receive Character Match Control 1 9001_101...

Page 391: ...CL OSE RXBYTES RL RS485OFF RS485ON DTREN RXFL USH RXEN TXEN M ODE Reserved RTSEN TXFL USH Reserv ed RTS Bits Access Mnemonic Reset Description D31 N A Reserved N A N A D30 R W RXEN 0 0 Disable wrapper...

Page 392: ...0 Idle or buffer already closed 1 Software initiated buffer close D12 N A Reserved N A N A D11 06 R W TXFLOW 010000 Selects which signals are routed to the UART for hardware flow control Transmit data...

Page 393: ...0 0 01 1 10 1 5 11 2 D01 00 R W RS485ON 00 RS485 transceiver assertion control In bit times before the falling edge of the start bit 00 0 01 1 10 1 5 11 2 Bits Access Mnemonic Reset Description 13 12...

Page 394: ...r close D13 R W CGAP 0 Enable character gap Enables interrupt generation when a character gap timeout event occurs D12 R W MATCH4 0 Enable character match4 Enables interrupt generation when a receive...

Page 395: ...on when the UART transmit FIFO indicates to the UART transmitter that a byte corresponds to a buffer close event D02 R W RBC 0 Enable receive buffer close Enables interrupt generation whenever a buffe...

Page 396: ...LOW 0 Enable overflow error Indicates that an overflow occurred in the UART s 4 character FIFO Note This should not happen in a properly configured system D18 R W1TC PARITY 0 Parity error Indicates th...

Page 397: ...7 R W1TC DSR 0 Data set ready Indicates that a state change has occurred on input signal DSR D06 R W1TC DCD 0 Data carrier detect Indicates that a state change has occurred in input signal DCD D05 R W...

Page 398: ...that the receiver has moved from the active state to the idle state The receiver moves from the active state to the idle state when a start bit has not been received after the previous stop bit Bits A...

Page 399: ...1018 9002_101C 9002_1020 9002_1024 9002_9014 9002_9018 9002_901C 9002_9020 9002_9024 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved STB W LS PE...

Page 400: ...to define the flow control characters If enabled this function s output is wired to the UART module instead of the CTS signal 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19...

Page 401: ...09 08 R W FLOW4 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 4 Note The ENABLE field has no effect on...

Page 402: ...pon match 11 Change the FLOW_STATE field to XOFF upon match D03 02 R W FLOW1 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Mat...

Page 403: ...enable Use this field to force the transmitter to send the character specified in the CHAR field D07 00 All user specified rules such as bit order parity or number of stop bits are enforced Write a 1...

Page 404: ...ccess Mnemonic Reset Description D31 01 R Not used 0 Write this field to 0 D00 R W ENABLE 0 Enable Write a 1 to this field to enable ARM wakeup control logic 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 2...

Page 405: ...a n s m i t B u f f e r Address 9001_1100 9001_9100 9002_1100 9002_9100 DLAB 0 Write UART Transmit Buffer is used for diagnostic purposes only Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28...

Page 406: ...ment U A R T B a ud R a t e D i v is o r MS B Address 9001_1104 9001_9104 9002_1104 9002_9104 DLAB 1 UART Baud Rate Divisor sets bits 15 08 of the baud rate generator divisor Bits Access Mnemonic Rese...

Page 407: ...on All other bits are for diagnostic purposes only Register Register bit assignment 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved BRDM Bits Ac...

Page 408: ...R W ELSI 0 Enables receive line status interrupt 0 Disabled 1 Enabled D01 R W ETBEI 0 Enables transmit holding register empty interrupt 0 Disabled 1 Enabled D00 R W ERBFI 0 Enables receive data avail...

Page 409: ...A R T L i n e C o n t r o l r e g i s t e r Address 9001_110C 9001_910C 9002_110C 9002_910C The UART Line Control register controls the UART settings 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27...

Page 410: ...s the Baud Rate Divisor MSB and LSB registers to be configured D06 R W SB 0 Set break if set TX data is set to 0 0 Disabled 1 Enabled D05 R W SP 0 Stick parity operates as follows When set bits 04 03...

Page 411: ...register This register is used for diagnostic purposes only 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved RTS Reserved LLB AFE DTR Bits Acces...

Page 412: ...eserved Reserved OE FE BI THRE DR FIER TEMT PE Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 R FIER N A RX FIFO error Indicates at least one parity framing or break error in t...

Page 413: ...N A Reflects the status of the ring indicator D05 R DSR N A Reflects the status of the data set ready input D04 R CTS N A Reflects the status of the clear to send input D03 R DDCD N A Delta DCD indic...

Page 414: ...S E R I A L C ON T RO L M O D U L E U ART UART Modem Status register 414 Hardware Reference NS9215...

Page 415: ...s zero stuffed that is if five consecutive ones occur independent of byte boundaries a zero is automatically inserted by the transmitter and automatically deleted by the receiver This allows a flag by...

Page 416: ...bort pattern seven consecutive ones if a transmit frame needs to be aborted prematurely The abort command takes effect on the next byte boundary and causes an FEh a zero followed by seven ones transmi...

Page 417: ...ata encoding Normal NRZ NRZI Biphase Level Manchester Biphase Space FM0 Biphase Mark FM1 Encoding examples This figure shows examples of the data encoding types In NRZI Biphase Space and Biphase Mark...

Page 418: ...6 counter that uses the transition timings on the receive data stream to adjust its count The DPLL adjusts the count so the DPLL output is placed properly in the bit cells to sample the receive data T...

Page 419: ...tee a minimum density of transitions the difference between the sending data rate and the DPLL output clock rate must be very small and depends on the longest possible run of zeros in the received fra...

Page 420: ...up the bit cell boundaries this corresponds to the subtract one and subtract two regions shown in the figure The DPLL makes no adjustment if the bit cell boundaries are lined up within one count of t...

Page 421: ...ry and the data transitions are at the center of the bit cell the DPLL operation is adjusted accordingly Decoding biphase mark or biphase space encoding requires that the data be sampled by both edges...

Page 422: ...r a t i o n r e g i s t e r Address 9002_9000 This is the primary Wrapper Configuration register Wrapper Configuration register RXEN 1 Enable Wrapper receive function TXEN 1 Enable Wrapper transmit fu...

Page 423: ...FIFO Write a 1 then a 0 to reset the FIFO D16 R W TXFLUSH 0 Resets the contents of the 64 byte TX FIFO Write a 1 then a 0 to reset the FIFO D15 14 R RXBYTES 00 Indicates how many bytes are pending in...

Page 424: ...1 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved TBC Reserv ed Not used VCRC RABORT HINT Reserv ed OFLOW ICRC RXCLS RBC TX_IDLE RX_IDLE Bits Access Mnemonic Rese...

Page 425: ...HDLC transmitter that a byte corresponds to a buffer close event D02 R W RBC 0 Enable receive buffer close Enables interrupt generation whenever a buffer close event is passed from the HDLC receiver t...

Page 426: ...n a properly configured system D18 R W1TC ICRC 0 Invalid CRC Indicates that a frame has been received with a CRC error D17 R W1TC VCRC 0 Valid CRC Indicates that a frame has been received with a valid...

Page 427: ...smitter has moved from the active state to the idle state The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out...

Page 428: ...23 22 21 20 19 18 17 16 30 Reserved HDATA Reserved Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W HDATA 0 Read Returns the contents of the receive buffer Write Used for...

Page 429: ...3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved CLK Reserved HDATA HDATA Not used HINT Bits Access Mnemonic Reset Description D31 08 R Not used 0 Write this field to 0 D07 06 R...

Page 430: ...hester data encoding for receiver and transmitter 110 Biphase Space data encoding for receiver and transmitter 111 Biphase Mark data encoding for receiver and transmitter D04 R W HMODE 0 HDLC mode 0 N...

Page 431: ...HDLC CLock Divider High register to set bits 14 08 of the clock divider Register HDLC rate bps 29 4912 MHz 16 x DIV 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 2 2 21 20 19 18 17 1...

Page 432: ...erence NS9215 Register bit assignment Bits Access Mnemonic Reset Description D31 08 R Not used 0 Write this field to 0 D07 R W EN 0 Clock enable Must be set when the internal clock is used D06 00 R W...

Page 433: ...ce SPI module Features DMA transfers to and from system memory Four wire interface RXD TXD CLK CS Multi drop supported through GPIO programming Master or slave operation High speed data transfer Maste...

Page 434: ...lel serial data conversion to stream serial data between memory and a peripheral The SPI port has no protocol associated with it other than transferring information in multiples of 8 bits Full duplex...

Page 435: ...er specifies the timing mode Timing modes Clocking mode diagrams The next two diagrams show the four SPI clocking modes SPI Mode0 and SPI Mode3 are the most commonly used modes SPI Mode0 and Mode3 fun...

Page 436: ...ammed in the DIVISOR field would be 0x016 The actual data rate would be 13 64 Mbps The general equation is DIVISOR round Up PLL output interface data rate In SPI slave mode In SPI slave mode the value...

Page 437: ...he fields available in any SDRAM specification are defined as follows Burst length 4 for 32 bit data bus 8 for 16 bit data bus Burst type Sequential CAS latency Component specific 2 or 3 OpMode Standa...

Page 438: ...eadConfig See the Memory Controller chapter 0x1c DynamictRP See the Memory Controller chapter Ox20 DynamictRAS See the Memory Controller chapter Ox24 DynamictSREX See the Memory Controller chapter Ox2...

Page 439: ...ister bit assignment Address Register 9003_1000 SPI Configuration register 9003_1010 Clock Generation register 9003_1020 Interrupt Enable register 9003_1024 Interrupt Status register 1 3 1 2 11 10 9 8...

Page 440: ...ytes before writing to the RX FIFO Write a 1 to RXBYTE The receiver writes to the RX FIFO each time a new byte is received This allows low latency handling of SPI receive data D02 R W BITORDR 0x0 Bit...

Page 441: ...i s t e r Address 9003_1020 13 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0 1 5 14 31 29 2 8 2 7 26 25 2 4 2 3 22 21 2 0 1 9 18 17 1 6 30 N otused N otused EN A BLE D ivisor Bit s Access Mnemonic Reset Divisor D31...

Page 442: ...26 25 24 23 22 21 20 19 18 17 16 30 Notused Notused TX_IDLE RX_IDLE Bits Access Mnemonic Reset Description D31 02 R W Not used 0 Write this field to 0 D01 R W TX_IDLE 0 Enable transmit idle Enables in...

Page 443: ...state The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data D00 R W1TC RX_IDLE 0 Receive idle Indicates th...

Page 444: ...not depend on the SPI master interface clock rate SPI master timing diagram SPI slave timing parameters Notes 1 The SPI slave interface clock duty cycle should be no worse than 60 40 Mode3 S1 Mode0 CS...

Page 445: ...a 7 5 Mhz SPI slave interface clock rate 3 The numbers shown here are for a 300 Mhz PLL output frequency This value must be proportionally increased with a PLL output frequency decrease 4 This paramet...

Page 446: ...S E R I A L C ON T RO L M O D U L E S PI SPI timing characteristics 446 Hardware Reference NS9215...

Page 447: ...slave are mutually exclusive P h y s i c a l I 2 C b u s The physical I2C bus consists of two open drain signal lines serial data SDA and serial clock SCL Pullup resistors are required see the standa...

Page 448: ...data line to preserve data integrity The number of ICs that can be connected to the same bus is limited only by a maximum bus capacity of 400 pf I 2 C e x t e r n a l a d d r e s s e s I2C external bu...

Page 449: ...for a list of commands If a command is sent to the master module that module is locked until a command acknowledgement is given Similarly if a command is sent to the slave module the slave module is l...

Page 450: ...it words and as single accesses only Bursting is not allowed After a reset all registers are set to the initial value If an unspecified register or bit is read a zero is returned C o m m a n d T r a n...

Page 451: ...PE 0x0 Pipeline mode Must be set to 0 D14 W DLEN 0x0 I2 C DLEN port iic_dlen Must be set to 0 D13 W TXVAL 0x0 Provide new transmit data in CMD_TX_DATA_REG tx_data_val D12 08 W CMD 0x0 Command to be se...

Page 452: ...DL N A Master command lock The Master Command register is locked D11 08 R IRQCD N A Interrupt codes irq_code The interrupt is cleared if this register is read See Interrupt Codes on page 455 for more...

Page 453: ...used Represents bits 9 0 of device address if using 10 bit address D00 R W MAM 0x0 Master addressing mode 07 bit address mode 110 bit address mode 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26...

Page 454: ...ke filtering can be applied to the received I2C data and clock signal The spike filter evaluates the incoming signal and suppresses spikes The maximum length of the suppressed spikes can be specified...

Page 455: ...Spike filter width A default value of 1 is recommended Available values are 0 15 D08 00 R W CLREF 0x0 clk_ref 9 1 The I2C clock on port iic_scl_out is generated by the system clock divided by the 10...

Page 456: ...level driver identifies one command S_STOP to discontinue a transaction After this command the slave remains inactive until the next start condition on the I2C bus If a slave is accessed by a master...

Page 457: ...a NO_ACK 4 STATUS_REG and RX_DATA_REG are read simultaneously host idle write optional M_ADDR_REG write cmd M_READ wait irq read rx status wait irq read rx status M_RX_DATA irq M_ARBIT_LOST irq M_NO_...

Page 458: ...mal mode 16 bit Note STATUS_REG and RX_DATA_REG are read simultaneously wait irq read rx status S_RX_DATA_1ST irq S_TX_DATA_1ST irq wait irq read rx status 1 S_RX_ABORT irq S_RX_DATA irq S_NO_ACK irq...

Page 459: ...Day of week from 1 7 Hour from 0 23 or from 1 12 with the AM PM flag set Minute from 0 59 Second from 0 00 59 99 RTC functionality also provides an alarm register that allows comparison of month date...

Page 460: ...n t r o l r e g i s t e r Address 9006 0000 The RTC General Control register contains miscellaneous settings for the RTC module Register Address Description 9006 0000 RTC General Control register 900...

Page 461: ...2 N A Reserved N A N A D01 R W Cal 0x1 Calendar operation 0 Calendar operation enabled 1 Calendar operation disabled D00 R W Time 0x1 Time date hour minute second operation 0 Time operation enabled 1...

Page 462: ...T M_U S_T S_U H_T H_U Bits Access Mnemonic Reset Description D31 N A Reserved N A N A D30 R W PM 0x0 PM Used in 12 hour mode only 0 AM 1 PM D29 28 R W HR_T 0x0 Hours tens BCD digit 0 2 D27 24 R W HR_U...

Page 463: ...16 30 Reserved Reserved C_T C_U Y_T Y_U D_U M_U D_T M_T Day Bits Access Mnemonic Reset Description D31 30 N A Reserved N A N A D29 28 R W C_T 0x0 Century tens BCD digit 1 2 D27 24 R W C_U 0x0 Century...

Page 464: ..._T H_U Bits Access Mnemonic Reset Description D31 N A Reserved N A N A D30 R W PM 0x0 PM Used in 12 hour mode only 0 AM 1 PM D29 28 R W HR_T 0x0 Hours tens BCD digit 0 2 D27 24 R W HR_U 0x0 Hours unit...

Page 465: ...sponding time unit trigger event Triggering the alarm causes an event to be generated as set in the Events Flag register If all fields are enabled an alarm is generated at the time set the specific mo...

Page 466: ...set 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved Mnth Date Hour Min Sec Hsec Bits Access Mnemonic Reset Description D31 06 N A Reserved N A N...

Page 467: ...rm Events register has triggered D05 R R Mnth Evnt 0x0 Month event 0 Month event has not occurred 1 Month event has occurred D04 R R Date Evnt 0x0 Date event 0 Date event has not occurred 1 Date event...

Page 468: ...Int Sec Int Hsec Int Alrm Int Bits Access Mnemonic Reset Description D31 07 N A Reserved N A N A D06 W Alrm Int 0x0 Alarm interrupt 0 Disable alarm interrupt 1 Enable alarm interrupt D05 W Mnth Int 0x...

Page 469: ...Reset Description D31 07 N A Reserved N A N A D06 W Alrm Dis 0x0 Alarm interrupt disable 0 Enable alarm interrupt 1 Disable alarm interrupt D05 W Mnth Dis 0x0 Month interrupt disable 0 Enable month in...

Page 470: ...Stat Hsec Stat Alrm Stat Bits Access Mnemonic Reset Description D31 07 N A Reserved N A N A D06 R Alrm Stat 1 Alarm interrupt status 0 Interrupt enabled 1 Interrupt disabled D05 R Mnth Stat 1 Month i...

Page 471: ...start operation Register Register bit assignment 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Reserved Reserved VCAC VTAC VCC VTC Bits Access Mnemonic Reset D...

Page 472: ...R E A L TI M E C L O C K M O D U L E General Status register 472 Hardware Reference NS9215...

Page 473: ...an external reference voltage which defines the full scale input range An analog multiplexer is included to enable the selection of up to eight inputs Features The ADC module supports these features 1...

Page 474: ...other selected channels The data buffer length must be a word multiple of the number of selected channels For example if three channels are selected the buffer length must be a multiple of three words...

Page 475: ...r at address 9003 9000 A D C c o n t r o l a nd s t a t u s r e g i s te r s The ADC configuration registers are located at offset 0x9003_9000 Register address map A D C C o n f i g u r a t i o n r e...

Page 476: ...INSTAT 0 Interrupt status Indicates the channel processed at the time of the interrupt D15 5 N A Reserved N A N A D04 R W INTCLR 0 Interrupt clear The ADC module generates an interrupt each time the A...

Page 477: ...Hz N value 10 ADC clock frequency ADC clock 299 8272 MHz 2 x 10 1 13 6285 MHz Wait states can be added to increase conversion time beyond 14 clock cycles Register Register bit assignment A D C O u t p...

Page 478: ...nce NS9215 Register Register bit assignment 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30 Not used DOUT Not used Bit s Access Mnemonic Reset Description D31 12...

Page 479: ...c s Absolute maximum ratings The processor operates at a 1 8V core with 3 3V I O ring voltages Permanent device damage can occur if absolute maximum ratings are ever exceeded Absolute maximum ratings...

Page 480: ...for I O and core Parameter Symbola a VDDA Ratings of I O cells for 3 3V interface VDDC Ratings of internal cells Rating Unit DC supply voltage VDDA 3 0 to 3 6 V VDDC core 1 62 to 1 98 V Maximum junct...

Page 481: ...he processor I O are 5 volt tolerant DC electrical inputs are provided below Sym Parameter Conditiona aVSS 0V GND Value Unit VIH High level input voltage LVTTL level Min 2 0 V VIL Low level input volt...

Page 482: ...may be registered incorrectly If the rise time of a positive edge triggered external interrupt is too slow then an interrupt may be detected on both the rising and falling edge of the input signal A m...

Page 483: ...evice Here are sample Schmitt trigger device part numbers Manufacturer Part Number Description Fairchild NC7SP17 Single Schmitt trigger buffer available in 5 lead SC70 and 6 lead MicroPak packages Phi...

Page 484: ...fers 3 Only one of the clk_out signals is used 4 Only one of the dy_cs_n signals is used Parm Description Min Max Unit Notes M1 data input setup time to rising 1 0 ns M2 data input hold time to rising...

Page 485: ...ad 16 bit Notes 1 This is the bank and RAS address 2 This is the CAS address pr e a ct rea d lat d A d B d C d D d E d F d G d H M 9 M 8 M 7 M 6 M 5 M1 1 M4 M2 M 1 N ot e 1 N o te 2 clk_ ou t da ta 3...

Page 486: ...6 bit CAS latency 3 Notes 1 This is the bank and RAS address 2 This is the CAS address pre act rea d la t la t d A d B d C d D d E d F d G d H M9 M 8 M7 M6 M5 M1 1 M 4 M 2 M 1 N ote 1 N ote 2 clk_ ou...

Page 487: ...Notes 1 This is the bank and RAS address 2 This is the CAS address pr e ac t w r d A d B d C d D d E d F d G d H M 9 M 8 M 7 M 6 M 5 M 5 M 4 M 12 M 1 0 N ote 1 No te 2 c lk _ ou t d ata 31 0 ad dr d...

Page 488: ...ead 32 bit Notes 1 This is the bank and RAS address 2 This is the CAS address prech g act ive re ad ca s lat da ta A dat a B da ta C d ata D M9 M 8 M7 M6 M 5 M 11 M 4 M2 M1 N ote 1 No te 2 clk_ ou t d...

Page 489: ...t CAS latency 3 Notes 1 This is the bank and RAS address 2 This is the CAS address p re a ct re ad lat la t da ta A d ata B da ta C d ata D M 9 M 8 M 7 M 6 M5 M1 1 M4 M 2 M 1 N o te 1 N o te 2 clk_ ou...

Page 490: ...9215 SDRAM burst write 32 bit Notes 1 This is the bank and RAS address 2 This is the CAS address prechg acti ve wr d A data B data C dat a D M9 M8 M7 M6 M5 M4 M12 M10 Note 1 Note 2 cl k_out data 31 0...

Page 491: ...TI MI NG Memory Timing www digiembedded com 491 SDRAM load mode M4 M9 M8 M7 M5 SD L dM d td op code clk_out dy_cs_n 3 0 ras_n cas_n we_n addr 11 0...

Page 492: ...TI M I NG Memory Timing 492 Hardware Reference NS9215 SDRAM refresh mode M9 M8 M7 M6 M6 M6 M6 clk_out dy_cs0_n dy_cs1_n dy_cs2_n dy_cs3_n ras_n cas_n we_n...

Page 493: ...TI MI NG Memory Timing www digiembedded com 493 Clock enable timing M13 M14 M3 clk_enable td clk_out clk_en 3 0 SDRAM cycle...

Page 494: ...nal buffer delays both address out and data in 10ns Parm Description Min Max Unit Notes M15 clock high to data out valid 2 2 ns M16 data out hold time from clock high 2 2 ns M17 clock high to address...

Page 495: ...WOEN 0 If the PB field is set to 1 all four byte_lane signals will go low for 32 bit 16 bit and 8 bit read cycles If the PB field is set to 0 the byte_lane signal will always be high M 24 M2 3 M 28 M...

Page 496: ...etermined by the WTRD field 2 The length of the 2nd 3rd and 4th cycles is determined by the WTPG field 3 This is the starting address The least significant two bits will always be 00 4 The least signi...

Page 497: ...15 WOEN from 0 to 15 If the PB field is set to 1 all four byte_lane signals will go low for 32 bit 16 bit and 8 bit read cycles If the PB field is set to 0 the byte_lane signal will always be high M24...

Page 498: ...er two byte_lane signals will go low During an 8 bit transfer only one byte_lane signal will go low Note If the PB field is set to 0 the byte_lane signals will function as write enable signals and the...

Page 499: ...lane signals will go low During an 8 bit transfer only one byte_lane signal will go low Note If the PB field is set to 0 the byte_lane signals will function as write enable signals and the we_n signal...

Page 500: ...gh one clock after we_n goes high 2 Timing of the we_n signal is determined with a combination of the WTWR and WWEN fields 3 Timing of the byte_lane signals is determined with a combination of the WTW...

Page 501: ...om clock high 2 2 ns M19 clock high to st_cs_n low 2 2 ns 2 M20 clock high to st_cs_n high 2 2 ns 2 M21 clock high to we_n low 2 2 ns M22 clock high to we_n high 2 2 ns M23 clock high to byte_lanes lo...

Page 502: ...wledge write M32 M26 M17 M18 M19 M20 M31 M27 M28 M23 M24 M29 M30 0ns 50ns 100ns 150ns 200ns clk_out data 31 0 addr 27 0 st_cs_n 3 0 oe_n byte_lane 3 0 ta_strb M15 M16 M17 M18 M19 M20 M31 M21 M22 M23 M...

Page 503: ...pf for all outputs and bidirects 3 Minimum specification is for fastest AHB clock at 88 5 MHz Ethernet MII timing Parm Description Min Max Unit Notes E1 MII tx_clk to txd tx_en tx_er 3 11 ns 2 E2 MII...

Page 504: ...timing diagram Standard Mode Fast Mode Parm Description Min Max Min Max Unit C1 iic_sda to iic_scl START hold time 4 0 0 6 C2 iic_scl low period 4 7 1 3 C3 iic_scl high period 4 7 1 3 C4 iic_scl to i...

Page 505: ...alid 10 ns 0 3 6 SP8 SPI CLK out rising to SPI data out valid 10 ns 1 2 6 SP9 SPI enable low hold from last SPI CLK out falling 3 TBCLK 10 2 ns 0 3 1 3 SP1O SPI enable low hold from last SPI CLK out r...

Page 506: ...hannel Control Register B is set to a 0 3 TBCLK is period of AHB clock 4 5 duty cycle skew 5 10 duty cycle skew 6 Cload 5pf for all outputs 7 SPI data order can be reversed such that LSB is first Use...

Page 507: ...PI data can be reversed such that LSB is first Use the BITORDER bit in Serial Channel B A C D Control Register A MSB LSB MSB LSB M SB LSB MSB LSB SP6 SP4 SP8 SP7 S 10 SP5 SP1 S9 SP1 2 SP1 2 SP1 3 SP1...

Page 508: ...data can be reversed such that LSB is first Use the BITORDER bit in Serial Channel B A C D Control Register A MS B LS B MS B LSB M S B LS B MS B LSB S P6 SP 4 SP 8 SP 7 S 10 S P5 SP 1 S 9 S P1 2 S P1...

Page 509: ...therwise noted The next table describes the values shown in the IEEE 1284 timing diagram Note The hardware strapping pins are latched 5 clock cycles after reset_n is deasserted goes high Parm Descript...

Page 510: ...m Notes 1 Maximum tck rate is 10 MHz 2 rtck_out is an asynchronous output driven off of the CPU clock 3 trst_n is an asynchronous input Parm Description Min Max Unit J1 tms input setup to tck rising 5...

Page 511: ...F unless otherwise noted System PLL reference clock timing The diagram below pertains to clock timing Parm Description Min Max Unit Notes SC1 x1_sys_osc cycle time 25 50 ns SC2 x1_sys_osc high time SC...

Page 512: ...TI M I NG Clock timing 512 Hardware Reference NS9215...

Page 513: ...513 Packaging C H A P T E R 1 7 Below is the processor package 265 LF XBGA Diagrams that follow show the processor dimensions top bottom and side views P a c k a g e...

Page 514: ...PA CKA GING Processor Dimensions 514 Hardware Reference NS9215 P r o c e s s o r D i m e n s i o n s...

Page 515: ...PA CKA GING Processor Dimensions www digiembedded com 515...

Page 516: ...PA CKA GING Processor Dimensions 516 Hardware Reference NS9215...

Page 517: ...d RTC clock and battery back up connection information Updated POR and battery backup logic information for situations when the POR feature is not used Added power dissipation data for 75MHz Deleted I...

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