Digi NS9215, Hardware Reference Manual, Page: 268 / 517

E T H E R N E T C O M M U N I C A T I O N M O D U L E
Receive packet processor
268
Hardware Reference NS9215
Transferring a
frame to system
memory
The
RX_RD
logic manages the transfer of a frame in the RX_FIFO to system memory.
The transfer is enabled by setting the
ERXDMA
(enable receive DMA) bit in Ethernet
General Control Register #1.
Transferring a frame in the receive FIFO to system memory begins when the
RX_WR
logic notifies the
RX_RD
logic that a good frame is in the receive FIFO. Frames are
transferred to system memory using up to four rings (that is, 1, 2, or 3 rings can also
be used) of buffer descriptors that point to buffers in system memory. The
maximum frame size that each ring can accept is programmable. The first thing the
RX_RD
logic does, then, is analyze the frame length in the receive status FIFO to
determine which buffer descriptor to use.
The
RX_RD
logic goes through the four buffer descriptors looking for the optimum
buffer size. It searches the enabled descriptors starting with A, then B, C, and
finally D; any pools that are full (that is, the F bit is set in the buffer descriptor) are
skipped. The search stops as soon as the logic encounters an available buffer that is
large enough to hold the entire receive frame.
The pointers to the first buffer descriptor in each of the four pools are found in the
related Buffer Descriptor Pointer register (RXAPTR, RXBPTR, RXCPTR, RXDPTR).
Pointers to subsequent buffer descriptors are generated by adding an offset of
0x10
from this pointer for each additional buffer used.
Receive buffer
descriptor format
Receive buffer
descriptor format
description
The current buffer descriptor for each pool is kept in local registers. The current
buffer descriptor registers are initialized to the buffer descriptors pointed to by the
Buffer Descriptor Pointer registers, by setting the
ERXINIT
(enable initialization of
RX
buffer descriptor registers) bit in Ethernet General Control Register #1. The
initialization process is complete when
RXINIT
(
RX
initialization complete) is set in
the Ethernet General Status register. At the end of a frame, the next buffer
descriptor for the ring just used is read from system memory and stored in the
registers internal to the
RX_RD
logic.
Destination Address (not used)
Buffer Length (11 lower bits used)
Status
Source Address
0
0
4
8
C
F I E W Reserved
31 15 16 30 29 28