Digi NS9215, Hardware Reference Manual, Page: 100 / 517

W O R K I N G W I T H T H E C P U
R9: Cache Lockdown register
100
Hardware Reference NS9215
Lockdown cache:
Specific loading of
addresses into a
cache-way
Use this procedure to lockdown cache. The procedure to lock down code and data
into way i of cache, with N ways, using format C, makes it impossible to allocate to
any cache way other than the target cache way:
1
Ensure that no processor exceptions can occur during the execution of this
procedure; for example, disable interrupts. If this is not possible, all code and
data used by any exception handlers must be treated as code and data as in
Steps 2 and 3.
2
If an ICache way is being locked down, be sure that all the code executed by
the lockdown procedure is in an uncachable area of memory or in an already
locked cache way.
3
If a DCache way is being locked down, be sure that all data used by the
lockdown procedure is in an uncachable area of memory or is in an already
locked cache way.
4
Ensure that the data/instructions that are to be locked down are in a cachable
area of memory.
5
Be sure that the data/instructions that are to be locked down are not already in
the cache. Use the Cache Operations register (R7) clean and/or invalidate
functions to ensure this.
6
Write these settings to the Cache Lockdown register (R9), to enable allocation
to the target cache way:
CRm = 0
Set L == 0 for bit i
Set L == 1 for all other bits
7
For each of the cache lines to be locked down in cache way i:
–
If a DCache is being locked down, use an
LDR
instruction to load a word from
the memory cache line to ensure that the memory cache line is loaded into the
cache.
–
If an ICache is being locked down, use the Cache Operations register (R7)
MCR
prefetch ICache line
(<CRm>==c13, <opcode2>==1)
to fetch the memory cache line
into the cache.
[3] L bit for way 3 Bits [3:0] are the L bits for each cache way:
0
Allocation to the cache way is determined by the standard
replacement algorithm (reset state)
1 No allocation is performed to this way
[2] L bit for way 2
[1] L bit for way 1
[0] L bit for way 0
Bits 4-way associative Notes