Digi NS9215, Hardware Reference Manual, Page: 119 / 517

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W O R K I N G W I T H T H E C P U
MMU faults and CPU aborts
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M M U f a u l t s a n d C P U a b o r t s
The MMU generates an abort on these types of faults:
Alignment faults (data accesses only)
Translation faults
Domain faults
Permission faults
In addition, an external abort can be raised by the external system. This can happen
only for access types that have the core synchronized to the external system:
Page walks
Noncached reads
Nonbuffered writes
Noncached read-lock-write sequence
(SWP)
Alignment fault
checking
Alignment fault checking is enabled by the A bit in the R1: Control register.
Alignment fault checking is not affected by whether the MMU is enabled.
Translation, domain, and permission faults are generated only when the MMU is
enabled.
The access control mechanisms of the MMU detect the conditions that produce
these faults. If a fault is detected as a result of a memory access, the MMU aborts
the access and signals the fault condition to the CPU core. The MMU retains status
and address information about faults generated by the data accesses in the Data
Fault Status register and Fault Address register (see “Fault Address and Fault Status
registers” on page 119).
The MMU also retains status about faults generated by instruction fetches in the
Instruction Fault Status register.
An access violation for a given memory access inhibits any corresponding external
access to the AHB interface, with an abort returned to the CPU core.
Fault Address and
Fault Status
registers
On a data abort, the MMU places an encoded four-bit value — the fault status —
along with the four-bit encoded domain number in the Data Fault Status register.
Similarly, on a prefetch abort, the MMU places an encoded four-bit value along with
the four-bit encoded domain number in the Instruction Fault Status register. In
addition, the MVA associated with the data abort is latched into the Fault Address