
. . . . .
W O R K I N G W I T H T H E C P U
R10:TLB Lockdown register
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101
8
Write
<CRm>==0
to Cache Lockdown register (R9), setting
L==1
for bit i and
restoring all other bits to the values they had before the lockdown routine was
started.
Cache unlock
procedure
To unlock the locked down portion of the cache, write to Cache Lockdown register
(R9) setting
L==0
for the appropriate bit. The following sequence, for example, sets
the L bit to 0 for way 0 of the ICache, unlocking way 0:
MRC p15, 0, Rn, c9, c0, 1;
BIC Rn, Rn, 0x01;
MCR p15, 0, Rn, c9, c0, 1;
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R 1 0 : T L B L o c k d o w n r e g i s t e r
The TLB Lockdown register controls where hardware page table walks place the TLB
entry — in the set associative region or the lockdown region of the TLB. If the TLB
entry is put in the lockdown region, the register indicates which entry is written.
The TLB lockdown region contains eight entries (see the discussion of the TLB
structure in "TLB structure," beginning on page 126, for more information).
Register format
P bit
When writing the TLB Lockdown register, the value in the P bit (D0) determines in
which region the TLB entry is placed:
Invalidate
operation
TLB entries in the lockdown region are preserved so invalidate-TLB operations only
invalidate the unpreserved entries in the TLB; that is, those entries in the set-
associative region. Invalidate-TLB single entry operations invalidate any TLB entry
corresponding to the modified virtual address given in
Rd
, regardless of the entry’s
preserved state; that is, whether they are in lockdown or set-associative TLB
regions. See “R8:TLB Operations register” on page 97 for a description of the TLB-
invalidate operations.
Victim
SBZ/UNP
31
28
25
29
26
0
SBZ
P
P=0
Subsequent hardware page table walks place the TLNB entry in the set associative region
of the TLB.
P=1
Subsequent hardware page table walks place the TLB entry in the lockdown region at the
entry specified by the victim, in the range 0–7.
Summary of Contents for NS9215
Page 1: ...NS9215 Hardware Reference 90000847_C Release date 10 April 2008...
Page 3: ......
Page 4: ......
Page 26: ...26 Hardware Reference NS9215...
Page 44: ...P I N O U T 26 5 System clock 44 Hardware Reference NS9215 System clock drawing...
Page 52: ...P I N O U T 26 5 Power and ground 52 Hardware Reference NS9215...
Page 80: ...I O C O N T ROL M O D U L E Memory Bus Configuration register 80 Hardware Reference NS9215...
Page 136: ...WOR KI N G W I TH T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215...
Page 202: ...S Y S T E M C O N T RO L M OD U L E RTC Module Control register 202 Hardware Reference NS9215...
Page 354: ...E X T E R N A L D M A DMA Peripheral Chip Select register 354 Hardware Reference NS9215...
Page 472: ...R E A L TI M E C L O C K M O D U L E General Status register 472 Hardware Reference NS9215...
Page 512: ...TI M I NG Clock timing 512 Hardware Reference NS9215...
Page 515: ...PA CKA GING Processor Dimensions www digiembedded com 515...
Page 516: ...PA CKA GING Processor Dimensions 516 Hardware Reference NS9215...