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15
Writing to other registers............................................................ 276
Ethernet Control and Status registers .................................................... 277
Register address filter................................................................ 277
Ethernet General Control Register #1 .................................................... 279
Ethernet General Control Register #2 .................................................... 282
Ethernet General Status register .......................................................... 283
Ethernet Transmit Status register......................................................... 284
Ethernet Receive Status register .......................................................... 286
MAC Configuration Register #1............................................................. 288
MAC Configuration Register #2............................................................. 289
PAD operation table for transmit frames.......................................... 291
Back-to-Back Inter-Packet-Gap register.................................................. 291
Non Back-to-Back Inter-Packet-Gap register ............................................ 292
Collision Window/Retry register........................................................... 293
Maximum Frame register ................................................................... 294
MII Management Configuration register .................................................. 295
Clocks field settings .................................................................. 296
MII Management Command register....................................................... 296
MII Management Address register ......................................................... 297
MII Management Write Data register...................................................... 298
MII Management Read Data register ...................................................... 298
MII Management Indicators register....................................................... 299
Station Address registers ................................................................... 300
Station Address Filter register ............................................................. 301
RegisterHash Tables ......................................................................... 302
HT1 ...................................................................................... 302
HT2 ...................................................................................... 303
Statistics registers ........................................................................... 303
Combined transmit and receive statistics counters address map ............. 303
Receive statistics counters address map .......................................... 304
Receive byte counter (A060 069C) ................................................. 304
Receive packet counter (A060 06A0) .............................................. 304
Receive FCS error counter (A060 06A4) ........................................... 305
Receive multicast packet counter (A060 06A8) .................................. 305
Receive broadcast packet counter (A060 06AC) ................................. 305
Receive control frame packet counter (A060 06B0) ............................. 305
Receive PAUSE frame packet counter (A060 06B4) .............................. 305
Receive unknown OPCODE packet counter (A060 06B8) ........................ 305
Receive alignment error counter (A060 06BC) ................................... 306
Receive code error counter (A060 06C4) .......................................... 306
Receive carrier sense error counter (A060 06C8) ................................ 306
Receive undersize packet counter (A060 06CC).................................. 306
Receive oversize packet counter (A060 06D0).................................... 306
Receive fragments counter (A060 06D4) .......................................... 306
Receive jabber counter (A060 06D8)............................................... 307
Summary of Contents for NS9215
Page 1: ...NS9215 Hardware Reference 90000847_C Release date 10 April 2008...
Page 3: ......
Page 4: ......
Page 26: ...26 Hardware Reference NS9215...
Page 44: ...P I N O U T 26 5 System clock 44 Hardware Reference NS9215 System clock drawing...
Page 52: ...P I N O U T 26 5 Power and ground 52 Hardware Reference NS9215...
Page 80: ...I O C O N T ROL M O D U L E Memory Bus Configuration register 80 Hardware Reference NS9215...
Page 136: ...WOR KI N G W I TH T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215...
Page 202: ...S Y S T E M C O N T RO L M OD U L E RTC Module Control register 202 Hardware Reference NS9215...
Page 354: ...E X T E R N A L D M A DMA Peripheral Chip Select register 354 Hardware Reference NS9215...
Page 472: ...R E A L TI M E C L O C K M O D U L E General Status register 472 Hardware Reference NS9215...
Page 512: ...TI M I NG Clock timing 512 Hardware Reference NS9215...
Page 515: ...PA CKA GING Processor Dimensions www digiembedded com 515...
Page 516: ...PA CKA GING Processor Dimensions 516 Hardware Reference NS9215...