
. . . . .
S Y S T E M C O N T R O L M O D U L E
System bus arbiter
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139
2
The arbiter stops evaluating the BRR until a bus grant is issued for the previous
evaluation cycle.
3
The arbiter grants the bus to requesting channels, in a round-robin manner, at
the rising clock edge of the last address issued for the current transaction (note
that each transaction may have multiple transfers), when a SPLIT response is
sampled by the arbiter, or when the bus is idling.
4
Each master samples the bus grant signal (
hgrant_x
) at the end of the current
transfer, as indicated by the
hready
signal. The bus master takes ownership of the
bus at this time.
5
The arbiter updates the
hmaster [3:0]
signals at the same time to indicate the
current bus master and to enable the new master’s address and control signals
to the system bus.
See your AMBA standards documentation for detailed information and illustrations
of AMBA AHB transactions.
Ownership
Ownership of the data bus is delayed from ownership of the address/control bus.
When
hready
indicates that a transfer is complete, the master that owns the
address/control bus can use the data bus — and continues to own that data bus —
until the transaction completes.
Note:
If a master is assigned more than one request/grant channel, these channels
need to be set and reset simultaneously to guarantee that a non-requesting
master will not occupy the system bus.
Locked bus
sequence
The arbiter observes the
hlock_x
signal from each master to allow guaranteed back-
to-back cycles, such as read-modified-write cycles. The arbiter ensures that no
other bus masters are granted the bus until the locked sequence has completed. To
support SPLIT or RETRY transfers in a locked sequence, the arbiter retains the bus
master as granted for an additional transfer to ensure that the last transfer in the
locked sequence completed successfully.
If the master is performing a locked transfer and the slave issues a split response,
the master continues to be granted the bus until the slave finishes the SPLIT
response. (This situation degrades AHB performance.)
Relinquishing the
bus
When the current bus master relinquishes the bus, ownership is granted to the next
requester.
If there are no new requesters, ownership is granted to the last master.
Bus parking must be maintained if other masters are waiting for SPLIT transfers
to complete.
Summary of Contents for NS9215
Page 1: ...NS9215 Hardware Reference 90000847_C Release date 10 April 2008...
Page 3: ......
Page 4: ......
Page 26: ...26 Hardware Reference NS9215...
Page 44: ...P I N O U T 26 5 System clock 44 Hardware Reference NS9215 System clock drawing...
Page 52: ...P I N O U T 26 5 Power and ground 52 Hardware Reference NS9215...
Page 80: ...I O C O N T ROL M O D U L E Memory Bus Configuration register 80 Hardware Reference NS9215...
Page 136: ...WOR KI N G W I TH T H E C P U Noncachable instruction fetches 136 Hardware Reference NS9215...
Page 202: ...S Y S T E M C O N T RO L M OD U L E RTC Module Control register 202 Hardware Reference NS9215...
Page 354: ...E X T E R N A L D M A DMA Peripheral Chip Select register 354 Hardware Reference NS9215...
Page 472: ...R E A L TI M E C L O C K M O D U L E General Status register 472 Hardware Reference NS9215...
Page 512: ...TI M I NG Clock timing 512 Hardware Reference NS9215...
Page 515: ...PA CKA GING Processor Dimensions www digiembedded com 515...
Page 516: ...PA CKA GING Processor Dimensions 516 Hardware Reference NS9215...